AU7077900A - Non-volatile memory structure for twin-bit storage and methods of making same - Google Patents

Non-volatile memory structure for twin-bit storage and methods of making same

Info

Publication number
AU7077900A
AU7077900A AU70779/00A AU7077900A AU7077900A AU 7077900 A AU7077900 A AU 7077900A AU 70779/00 A AU70779/00 A AU 70779/00A AU 7077900 A AU7077900 A AU 7077900A AU 7077900 A AU7077900 A AU 7077900A
Authority
AU
Australia
Prior art keywords
twin
methods
volatile memory
memory structure
making same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU70779/00A
Inventor
Yao-Wen Chang
Tao Cheng Lu
Hsiang Lan Lung
Der Shin Shyu
Mam Tsung Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix America Inc
Original Assignee
Macronix America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix America Inc filed Critical Macronix America Inc
Publication of AU7077900A publication Critical patent/AU7077900A/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AU70779/00A 1999-08-27 2000-09-19 Non-volatile memory structure for twin-bit storage and methods of making same Abandoned AU7077900A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US38489699A 1999-08-27 1999-08-27
US09384896 1999-08-27
PCT/US2000/023484 WO2001017030A1 (en) 1999-08-27 2000-08-25 Non-volatile memory structure for twin-bit storage and methods of making same

Publications (1)

Publication Number Publication Date
AU7077900A true AU7077900A (en) 2001-03-26

Family

ID=23519196

Family Applications (1)

Application Number Title Priority Date Filing Date
AU70779/00A Abandoned AU7077900A (en) 1999-08-27 2000-09-19 Non-volatile memory structure for twin-bit storage and methods of making same

Country Status (4)

Country Link
JP (1) JP2003508920A (en)
CN (1) CN1376313A (en)
AU (1) AU7077900A (en)
WO (1) WO2001017030A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1246196B1 (en) 2001-03-15 2010-02-17 Halo, Inc. Twin MONOS memory cell usage for wide program bandwidth
EP1300888B1 (en) 2001-10-08 2013-03-13 STMicroelectronics Srl Process for manufacturing a dual charge storage location memory cell
EP1313149A1 (en) 2001-11-14 2003-05-21 STMicroelectronics S.r.l. Process for fabricating a dual charge storage location memory cell
DE10201304A1 (en) 2002-01-15 2003-07-31 Infineon Technologies Ag Non-volatile semiconductor memory cell and associated manufacturing process
DE10205079B4 (en) * 2002-02-07 2008-01-03 Infineon Technologies Ag Method for producing a memory cell
JP2004056089A (en) * 2002-05-31 2004-02-19 Sharp Corp Ic card
US7042045B2 (en) * 2002-06-04 2006-05-09 Samsung Electronics Co., Ltd. Non-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure
DE10238784A1 (en) * 2002-08-23 2004-03-11 Infineon Technologies Ag Non-volatile semiconductor memory element and associated manufacturing and control method
US6795342B1 (en) * 2002-12-02 2004-09-21 Advanced Micro Devices, Inc. System for programming a non-volatile memory cell
JP2004247436A (en) 2003-02-12 2004-09-02 Sharp Corp Semiconductor memory, display device, and mobile apparatus
JP2004342889A (en) 2003-05-16 2004-12-02 Sharp Corp Semiconductor memory, semiconductor device, method of manufacturing semiconductor memory, and portable electronic equipment
JP2004348818A (en) 2003-05-20 2004-12-09 Sharp Corp Method and system for controlling writing in semiconductor memory device, and portable electronic device
JP2004348815A (en) 2003-05-20 2004-12-09 Sharp Corp Driver circuit of semiconductor memory device and portable electronic device
JP4480955B2 (en) 2003-05-20 2010-06-16 シャープ株式会社 Semiconductor memory device
JP2004349355A (en) 2003-05-20 2004-12-09 Sharp Corp Semiconductor storage device, its redundancy circuit, and portable electronic equipment
JP2004348817A (en) 2003-05-20 2004-12-09 Sharp Corp Semiconductor memory device, its page buffer resource allotting method and circuit, computer system, and portable electronic equipment
JP2004349308A (en) * 2003-05-20 2004-12-09 Sharp Corp Semiconductor memory device
US6903967B2 (en) * 2003-05-22 2005-06-07 Freescale Semiconductor, Inc. Memory with charge storage locations and adjacent gate structures
US7238974B2 (en) 2004-10-29 2007-07-03 Infineon Technologies Ag Semiconductor device and method of producing a semiconductor device
WO2006045278A1 (en) * 2004-10-29 2006-05-04 Infineon Technologies Ag Semiconductor circuit arrangement and method for producing a semiconductor circuit arrangement
JP2007110024A (en) * 2005-10-17 2007-04-26 Sharp Corp Semiconductor memory device
AU2012297589C1 (en) 2011-12-22 2015-04-16 Nuvo Research Gmbh Liposomal compositions
US9847133B2 (en) * 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408115A (en) * 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device
JP2910647B2 (en) * 1995-12-18 1999-06-23 日本電気株式会社 Manufacturing method of nonvolatile semiconductor memory device
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Also Published As

Publication number Publication date
WO2001017030A1 (en) 2001-03-08
CN1376313A (en) 2002-10-23
JP2003508920A (en) 2003-03-04

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase