AU2001245914A1 - Method for forming a silicide gate stack for use in a self-aligned contact etch - Google Patents

Method for forming a silicide gate stack for use in a self-aligned contact etch

Info

Publication number
AU2001245914A1
AU2001245914A1 AU2001245914A AU4591401A AU2001245914A1 AU 2001245914 A1 AU2001245914 A1 AU 2001245914A1 AU 2001245914 A AU2001245914 A AU 2001245914A AU 4591401 A AU4591401 A AU 4591401A AU 2001245914 A1 AU2001245914 A1 AU 2001245914A1
Authority
AU
Australia
Prior art keywords
self
forming
gate stack
aligned contact
contact etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001245914A
Inventor
Max F. Hineman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001245914A1 publication Critical patent/AU2001245914A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
AU2001245914A 2000-03-23 2001-03-22 Method for forming a silicide gate stack for use in a self-aligned contact etch Abandoned AU2001245914A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09533697 2000-03-23
US09/533,697 US6638843B1 (en) 2000-03-23 2000-03-23 Method for forming a silicide gate stack for use in a self-aligned contact etch
PCT/US2001/009054 WO2001071800A2 (en) 2000-03-23 2001-03-22 Method for forming a silicide gate stack for use in a self-aligned contact etch

Publications (1)

Publication Number Publication Date
AU2001245914A1 true AU2001245914A1 (en) 2001-10-03

Family

ID=24127071

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001245914A Abandoned AU2001245914A1 (en) 2000-03-23 2001-03-22 Method for forming a silicide gate stack for use in a self-aligned contact etch

Country Status (7)

Country Link
US (3) US6638843B1 (en)
JP (1) JP2004502295A (en)
KR (1) KR100626928B1 (en)
AU (1) AU2001245914A1 (en)
DE (1) DE10195958T1 (en)
TW (1) TW493222B (en)
WO (1) WO2001071800A2 (en)

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US6583003B1 (en) * 2002-09-26 2003-06-24 Sharp Laboratories Of America, Inc. Method of fabricating 1T1R resistive memory array
US6977408B1 (en) * 2003-06-30 2005-12-20 Lattice Semiconductor Corp. High-performance non-volatile memory device and fabrication process
CN100352006C (en) * 2003-11-18 2007-11-28 南亚科技股份有限公司 Manufacturing method of gate pole structure with metal layer lateral surface part removed
US20070087565A1 (en) * 2005-10-18 2007-04-19 Marcus Culmsee Methods of forming isolation regions and structures thereof
KR100654000B1 (en) * 2005-10-31 2006-12-06 주식회사 하이닉스반도체 Method of manufacturing semiconductor device having metal silicide layer
US8754483B2 (en) * 2011-06-27 2014-06-17 International Business Machines Corporation Low-profile local interconnect and method of making the same
US20140073106A1 (en) 2012-09-12 2014-03-13 International Business Machines Corporation Lateral bipolar transistor and cmos hybrid technology
US8728927B1 (en) * 2012-12-10 2014-05-20 International Business Machines Corporation Borderless contacts for semiconductor transistors
US9633860B2 (en) * 2015-07-09 2017-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same
US10546785B2 (en) 2017-03-09 2020-01-28 International Business Machines Corporation Method to recess cobalt for gate metal application
US11239115B2 (en) 2019-10-30 2022-02-01 International Business Machines Corporation Partial self-aligned contact for MOL

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US5206187A (en) 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop
JPH0595113A (en) * 1991-10-01 1993-04-16 Hitachi Ltd Semiconductor device and its manufacture
US5258096A (en) 1992-08-20 1993-11-02 Micron Semiconductor, Inc. Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths
US5372673A (en) 1993-01-25 1994-12-13 Motorola, Inc. Method for processing a layer of material while using insitu monitoring and control
US5338700A (en) * 1993-04-14 1994-08-16 Micron Semiconductor, Inc. Method of forming a bit line over capacitor array of memory cells
JP3262434B2 (en) * 1993-12-27 2002-03-04 株式会社東芝 Method for manufacturing semiconductor device
US5434093A (en) * 1994-08-10 1995-07-18 Intel Corporation Inverted spacer transistor
US5597746A (en) 1995-08-09 1997-01-28 Micron Technology, Inc. Method of forming field effect transistors relative to a semiconductor substrate and field effect transistors produced according to the method
US5804506A (en) 1995-08-17 1998-09-08 Micron Technology, Inc. Acceleration of etch selectivity for self-aligned contact
US5897372A (en) 1995-11-01 1999-04-27 Micron Technology, Inc. Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer
US5981383A (en) * 1996-03-18 1999-11-09 United Microelectronics Corporation Method of fabricating a salicide layer of a device electrode
JP2836569B2 (en) * 1996-03-28 1998-12-14 日本電気株式会社 Dry etching method
US5783496A (en) 1996-03-29 1998-07-21 Lam Research Corporation Methods and apparatus for etching self-aligned contacts
US5915181A (en) 1996-07-22 1999-06-22 Vanguard International Semiconductor Corporation Method for forming a deep submicron MOSFET device using a silicidation process
JPH1050992A (en) * 1996-08-01 1998-02-20 Toshiba Corp Semiconductor device, fabrication thereof and memory cell employing semiconductor device
US5688706A (en) 1996-08-01 1997-11-18 Vanguard International Semiconductor Corporation Method for fabricating a MOSFET device, with local channel doping, self aligned to a selectively deposited tungsten gate
JPH10144915A (en) * 1996-11-05 1998-05-29 Fujitsu Ltd Semiconductor device and its manufacturing method
US5854135A (en) * 1997-04-09 1998-12-29 Vanguard International Semiconductor Corporation Optimized dry etching procedure, using an oxygen containing ambient, for small diameter contact holes
US5880019A (en) 1997-04-17 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Insitu contact descum for self-aligned contact process
US6849557B1 (en) * 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
JPH113997A (en) * 1997-06-10 1999-01-06 Sony Corp Manufacture of semiconductor device
JP3232043B2 (en) * 1997-06-30 2001-11-26 株式会社東芝 Method for manufacturing semiconductor device
US5948701A (en) 1997-07-30 1999-09-07 Chartered Semiconductor Manufacturing, Ltd. Self-aligned contact (SAC) etching using polymer-building chemistry
US6130137A (en) * 1997-10-20 2000-10-10 Micron Technology, Inc. Method of forming a resistor and integrated circuitry having a resistor construction
US6165910A (en) * 1997-12-29 2000-12-26 Lam Research Corporation Self-aligned contacts for semiconductor device
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US6291330B1 (en) * 2000-01-31 2001-09-18 United Microelectronics Corp. Method of fabricating gate structure to reduce stress production
US6316323B1 (en) * 2000-03-21 2001-11-13 United Microelectronics Corp. Method for forming bridge free silicide by reverse spacer

Also Published As

Publication number Publication date
WO2001071800A2 (en) 2001-09-27
US6638843B1 (en) 2003-10-28
JP2004502295A (en) 2004-01-22
WO2001071800A3 (en) 2002-03-07
DE10195958T1 (en) 2003-08-28
TW493222B (en) 2002-07-01
US20020160595A1 (en) 2002-10-31
US20010053595A1 (en) 2001-12-20
KR20030062228A (en) 2003-07-23
KR100626928B1 (en) 2006-09-20

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