JPH11284186A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and method for manufacturing it wherein, comprising self-align contact structure and silicide structure, wiring density is raised for more fineness. SOLUTION: The semiconductor device comprises a gate electrode layer 16 which, formed on a main surface of a silicon substrate 10 with a gate insulating layer 14 in between, comprises a doped polysilicon layer, impurity diffusion layers 20a and 20b formed on a main-surface surface part of the silicon substrate, a first metal silicide layer 18 formed on the surface of the gate electrode layer, second metal silicide layers 22a and 22b formed on the surface of the impurity diffusion layer, an insulating layer 300 formed on the surface of the gate electrode layer and the first metal silicide layer, an inter layer insulating layer 100 with a contact hole CH where at least a part of the impurity diffusion layer is exposed formed with the insulating layer 300 as a mask, and a wiring layer 50 formed inside the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a self-aligned contact structure and a silicide structure, and a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, with miniaturization of a MOS transistor, the resistance of an impurity diffusion layer forming a source region or a drain region (source / drain region) of a transistor becomes smaller than a channel resistance. There is a delay due to the relative increase. As one method for solving this problem, a MOS transistor using salicide technology has been developed.

A salicide MOS transistor is a transistor in which a metal silicide layer is formed in a self-aligning manner on the surface of a polysilicon layer forming a gate electrode and an impurity diffusion layer forming source / drain regions, thereby reducing the resistance. is there.

In a semiconductor device having such a silicide structure, contact between an impurity diffusion layer and a wiring layer is made through a contact hole formed in an interlayer insulating layer. At this time, in order to secure insulation between the conductive layer in the contact hole and the gate electrode, a margin for mask alignment is required at the time of forming the contact hole, which is one of the factors that hinder miniaturization of the element. Has become.

An object of the present invention is to provide a semiconductor device having a self-aligned contact structure and a silicide structure, capable of increasing the wiring density and achieving further miniaturization, and a method of manufacturing the same.

[0006]

A method of manufacturing a semiconductor device according to the present invention includes the following steps (a) to (h).

(A) forming a conductive layer containing silicon in a predetermined region on a main surface of a silicon substrate via an insulating layer;
(B) a step of forming a first sidewall insulating layer on a side surface of the conductive layer; (c) a step of forming an impurity diffusion layer on a main surface of the silicon substrate; (d) the conductive layer and the impurity diffusion Forming a metal silicide layer in a self-aligned manner on the surface of the layer, (e) covering the surfaces of the conductive layer and the metal silicide layer on the conductive layer, and electrically insulating the conductive layer and the metal silicide layer Forming an insulating layer, (f) forming an interlayer insulating layer, and (g) using the first sidewall insulating layer and the insulating layer as a mask while at least a part of the impurity diffusion layer is exposed. Forming contact holes in a self-aligned manner,
And (h) forming a wiring layer in the contact hole.

In this manufacturing method, the step (g)
A contact hole can be formed in the first interlayer insulating layer in a self-aligned manner using the first sidewall insulating layer covering the conductive layer and the insulating layer as a mask, so that a contact hole is formed. It is not necessary to consider an alignment error in lithography at the time, and the wiring density can be improved. Further, in the step (d), a metal silicide layer is formed in a self-aligned manner on the surface of the conductive layer and the impurity diffusion layer, so that the resistance of the conductive layer and the impurity diffusion layer can be reduced while miniaturizing the device. Can be reduced.

As described above, according to the manufacturing method of the present invention,
The salicide technique and the self-aligned contact technique can be combined, so that the wiring density can be reduced and the element can be miniaturized. Specifically, the conductive layer is at least one of a gate electrode layer including a gate electrode, and a wiring layer at least partially existing on the element isolation region.

The insulating layer formed in the step (e) may be formed by forming an upper insulating layer on an upper surface of the metal silicide layer on the conductive layer, and then forming the upper insulating layer on the first sidewall insulating layer and the upper insulating layer. Desirably, it is obtained by forming a second sidewall insulating layer on the side surface of the layer. By forming the second sidewall insulating layer, it is possible to compensate for an alignment error generated at the time of forming the mask of the upper insulating layer, and to form an insulating layer capable of reliably performing electrical insulation.

The insulating layer formed in the step (e) is preferably 800 ° C. or lower, more preferably 250 to
It is formed at a temperature of 700 ° C. As described above, by forming the insulating layer at a relatively low temperature, the film quality of the metal silicide layer formed in the step (d), particularly the conductivity, can be maintained well.

A semiconductor device obtained by the manufacturing method of the present invention is formed on a main surface of a silicon substrate with an insulating layer interposed therebetween, a conductive layer containing silicon, and an impurity diffusion formed on a surface portion of the main surface of the silicon substrate. A first metal silicide layer formed on the surface of the conductive layer, a second metal silicide layer formed on the surface of the impurity diffusion layer, and an insulating layer formed on the surface of the conductive layer and the first metal silicide layer. A contact layer formed with a contact hole exposing at least a part of the impurity diffusion layer; and a wiring layer formed in the contact hole.

The semiconductor device and the method of manufacturing the same according to the present invention can be applied to a device having a structure having a contact portion with the impurity diffusion layer while securing insulation between the conductive layer and the impurity diffusion layer. As such a semiconductor device, for example, SRAM, DRAM, E ² PRO
M, Flash E ² PROM, and the like, or an LSI product made by combining them.

[0014]

(First Embodiment) FIG. 6 is a partial cross-sectional view schematically showing one example of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a gate insulating layer 14 formed on a silicon substrate 10 and a gate electrode layer 1 formed on the gate insulating layer 14.
6, 16; first sidewall insulating layers 30 formed on both sides of the stacked body of each gate insulating layer 14 and gate electrode 16; and impurities constituting source / drain regions formed on the surface of the silicon substrate 10. Diffusion layer 20
a and 20b. Then, the impurity diffusion layer 20
a, 20b, and the surface of the gate electrode layer 16,
Silicide layer (second metal silicide layer) 22 of a metal such as titanium, cobalt, nickel, tungsten, and chromium
a, 22b and the first metal silicide layer 18 are formed.

The present embodiment is characterized in that the gate electrode layer 16 and the first sidewall insulating layer 3
That is, an insulating layer is further provided on the upper part of the O. This insulating layer includes an upper insulating layer 32 formed so as to cover the upper surface of the gate electrode layer 16 and the first sidewall insulating layer 3.
0 and a second sidewall insulating layer 34 formed continuously on both sides of the upper insulating layer 32.
A state where the surfaces of the gate electrode layer 16 and the first metal silicide layer 18 are completely covered by the insulating layer 300 including the first sidewall insulating layer 30, the upper insulating layer 32, and the second sidewall insulating layer 34. Become.

An interlayer insulating layer 100 made of a silicon oxide film containing an impurity such as PBSG or PSG is formed on the surface of the substrate on which the above-described elements are formed. This interlayer insulating layer 100 includes adjacent gate insulating layers 16 and 16.
And a contact hole CH in which the impurity diffusion layer 22a located between the insulating layers 300 and 300 is exposed. In the contact hole CH, a wiring made of a barrier layer 52 and a metal layer 54 of aluminum or an alloy thereof is used. A layer 50 has been formed.

In the semiconductor device shown in FIG. 6, metal silicide layers 22a, 22b and 18 are formed on the surfaces of gate electrode layer 16 and impurity diffusion layers 20a and 20b to reduce the resistance of these conductive layers. . Also,
The gate electrode layer 16 and the first metal silicide layer 18
The contact holes C are electrically insulated by the insulating layer 300 and are self-aligned using the insulating layer 300 as a mask.
Since H can be formed, it is possible to form the wiring layer 50 that can be miniaturized while ensuring reliable electrical connection.

(Manufacturing Process) Next, a method of manufacturing the above-described semiconductor device will be described with reference to FIGS.

(A) First, as shown in FIG. 1, gate insulating layers 14 and 14 and gate electrode layers 16 and 16 made of polysilicon doped with impurities are formed on a silicon substrate 10. Further, a first sidewall insulating layer 30 is formed on both sides of the gate insulating layer 14 and the gate electrode layer 16, and impurity diffusion layers 20a and 20b forming source / drain regions are formed in the silicon substrate 10, thereby forming a MOS element. I do. It is desirable that the source / drain regions have an LDD structure. The manufacturing method of the MOS element is not particularly limited, and the MOS element can be formed by a generally used method.

(B) Next, a metal layer having a thickness of, for example, 5 to 100 nm is formed on the surface of the substrate on which the MOS elements are formed by sputtering. This metal layer is desirably selected from metals capable of forming silicide, such as titanium, cobalt, tungsten, chromium and nickel.

Subsequently, a heat treatment for silicidation is performed to form contact portions between the impurity diffusion layers 20a and 20b and the metal layer, and the gate electrode layer 1 made of polysilicon.
6 and the metal layer, the metal silicide layer 22
a, 22b and 18 are formed. The heat treatment for silicidation is performed, for example, at 550 to 800 ° C. for about 5 to 60 seconds. Next, etching is performed, for example, at room temperature to 85 ° C. for about 30 seconds to 20 minutes using an etchant containing ammonia-hydrogen peroxide as a main component, and the unreacted metal film is removed by self-alignment. As a result, as shown in FIG. 2, metal silicide layers 22a and 22b are formed on the surfaces of impurity diffusion layers 20a and 20b, and a first metal silicide layer 18 is formed on the surface of gate electrode layer 16.

As the etchant, in addition to the above etchant, a material obtained by adding a hydrogen peroxide solution to sulfuric acid or hydrochloric acid depending on the material of the unreacted metal or the like can be applied.

Next, the metal silicide layers 22a, 22
Further heat treatment is performed to stabilize b and 18.
In this case, the heat treatment is performed at, for example,
This is performed for about 60 seconds.

(C) Then, as shown in FIG. 3, the surface of the substrate is preferably 800 ° C. or less, more preferably 25 ° C.
Under a temperature condition of 0 to 700 ° C., an insulating layer such as a silicon oxide film or a silicon nitride film is
Deposit with a thickness of 500 μm. As described above, by forming the insulating layer at a relatively low temperature, the film quality, particularly conductivity, of the metal silicide layers 22a, 22b, and 18 formed in the step (b) can be maintained well.

Next, photolithography and RIE
The upper insulating layer 32 is formed on the gate electrode layer 16 by dry etching. The upper insulating layer 32 is desirably formed so as to almost completely cover the surface of the first metal silicide layer 18 exposed at the gate electrode portion.

(D) Then, as shown in FIG. 4, the surface of the substrate is preferably 800 ° C. or less, more preferably 25 ° C.
Under a temperature condition of 0 to 700 ° C., an insulating layer such as a silicon oxide film or a silicon nitride film is
Deposit with a thickness of 500 μm. The temperature condition in this film forming step is set for the same reason as in the above step (c). Next, a second sidewall insulating layer 34 is formed on both sides of the first sidewall insulating layer 30 and the upper insulating layer 32 by isotropic etching such as RIE. This second
The side wall insulating layer 34 is formed in consideration of a case where the upper insulating layer 32 formed in the step (c) is not formed so as to completely cover the entire surface of the first metal silicide layer 18 due to an alignment error or the like. The second sidewall insulating layer 34 is formed on both sides of the first sidewall insulating layer 30 and the upper insulating layer 32, so that the periphery of the gate electrode layer 16 can be electrically insulated. That is, the upper insulating layer 32 and the second sidewall insulating layer 34 only need to ensure such insulation properties, and their shapes and film thicknesses are set from the viewpoint of the insulation properties.

As described above, the first sidewall insulating layer 3
0, upper insulating layer 32 and second sidewall insulating layer 3
4 to form a contact hole in the next step.
By using 00 as a mask, a contact hole can be formed in a self-aligned manner.

(E) Next, for example, by a CVD method using tetraethoxysilane, for example, a film thickness of 30 to 1000 n
The m interlayer insulating layers 100 are formed. Next, a contact hole CH is formed at a predetermined position of the interlayer insulating layer 100, that is, in this embodiment, such that the impurity diffusion layer 20a located between the adjacent gate wiring layers 16, 16 is exposed. At this time, as described above, the gate electrode layer 1
6 and the insulating layer 300 covering the periphery of the first metal silicide layer 18, the contact hole CH can be formed in a self-aligned manner.

The contact hole CH is formed by RIE using the resist layer RE and the insulating layer 300 patterned by photolithography as a mask.
It is formed by etching with, for example,. At this time, since the insulating layer 300 functions as a mask, there is no need to consider the alignment error of the resist layer RE, and the contact holes CH can be formed in a self-aligned manner. Can be.

(F) Next, as shown in FIG. 6, a barrier layer 52 and a metal layer 54 are formed in the contact hole CH by sputtering. Thereafter, by patterning the barrier layer 52 and the metal layer 54 by photolithography and dry etching, the wiring layer 5 is formed.
0 can be formed. The barrier layer 52 is preferably, for example, a metal nitride selected from titanium, tungsten, cobalt, nickel, or the like, or a laminated film of a metal film and a metal nitride film. Further, as the metal layer 54, for example, aluminum, copper, nickel, gold, silver, an alloy thereof, a compound containing silicon as a main component, or the like can be used.

As the metal layer 54, although not shown, a plug is formed by depositing a refractory metal such as tungsten or molybdenum or a silicide of these metals in the contact hole CH, and then forming aluminum, copper, or the like. A metal layer mainly containing a metal such as gold or silver may be formed.

(Second Embodiment) FIG. 7 is a partial sectional view of a semiconductor device according to a second embodiment. 7, portions having substantially the same functions as the members shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, the formation region of the contact hole CH is different from that of the first embodiment. That is, in the first embodiment, an example in which a contact hole is formed in a self-aligned manner between adjacent gate electrode layers has been described. However, in this embodiment, only one side of the contact hole CH has a gate electrode. The difference from the first embodiment is that a layer is formed.

In FIG. 7, reference numeral 60 denotes the impurity diffusion layer 2.
The element isolation region adjacent to 0a is shown. In this embodiment, as in the first embodiment, the contact holes CH are formed in a self-aligned manner using the insulating layer 300 formed around the gate electrode layer 16 and the first metal silicide layer 18 as a mask. Therefore, the wiring density can be increased.

(Third Embodiment) FIG. 8 is a partial sectional view of a semiconductor device according to a third embodiment. 8, portions having substantially the same functions as the members of the semiconductor device shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, the wiring layer 70 formed on the element isolation region 60 instead of the gate electrode layer
The second embodiment is different from the second embodiment in that a metal silicide layer 72 formed on the wiring layer 70 is provided. In this embodiment, a metal silicide layer 72 is formed on the surface of a wiring layer 70 composed of a conductor in which an impurity is doped into polysilicon by the method described above. Similarly, a metal silicide layer 22 is also formed on the surface of the impurity diffusion layer 20. Then, the wiring layer 70
1st sidewall insulating layer 3 formed on both sides of
0, the upper insulating layer 32 formed on the surface of the metal silicide layer 72, and the second sidewall insulating layers 34 formed on both sides of the first sidewall insulating layer 30 and the upper insulating layer 32, to form the wiring layer 70 and Insulating layer 300 for electrically insulating the periphery of metal silicide layer 72
Are formed.

In this embodiment, as in the first embodiment, a contact hole CH is formed in the wiring layer 70.
And insulating layer 3 formed around metal silicide layer 72
Since the wirings can be formed in a self-aligned manner using the mask 00 as a mask, wiring density can be increased.

The present invention is not limited to the above-described embodiment, and the present invention is not limited to the above-described embodiment in which insulation between a conductive layer such as a gate electrode layer or a wiring layer and an impurity diffusion layer provided adjacent to the conductive layer is ensured. The present invention can be applied to a device having a structure having a contact portion with an impurity diffusion layer.

[0039]

[Brief description of the drawings]

FIG. 1 is a partial sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a partial sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a partial cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a partial cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a partial cross-sectional view illustrating the method for manufacturing the semiconductor device and the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a partial sectional view of a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate 14 Gate insulating layer 16 Gate electrode layer 18 1st metal silicide layer 20a, 20b Impurity diffusion layer 22a, 22b 2nd metal silicide layer 30 1st sidewall insulating layer 32 Upper insulating layer 34 2nd sidewall insulating layer 300 Insulating layer 50 Wiring layer 52 Barrier layer 54 Metal layer 60 Element isolation region 70 Wiring layer 72 Metal silicide layer

Claims (9)

[Claims] A conductive layer containing silicon formed on a main surface of a silicon substrate via an insulating layer; an impurity diffusion layer formed on a surface portion of the main surface of the silicon substrate; and a conductive layer formed on a surface of the conductive layer. A first metal silicide layer, a second metal silicide layer formed on the surface of the impurity diffusion layer, an insulating layer formed on the surface of the conductive layer and the first metal silicide layer, at least a part of the impurity diffusion layer. A semiconductor device, comprising: an interlayer insulating layer in which a contact hole exposing a contact hole is formed; and a wiring layer formed in the contact hole. 2. The semiconductor device according to claim 1, wherein the conductive layer is a gate electrode layer including a gate electrode. 3. The semiconductor device according to claim 1, wherein at least a part of the conductive layer is a wiring layer existing on an element isolation region. 4. The insulating layer according to claim 1, wherein the insulating layer is a first sidewall insulating layer formed on a side surface of the conductive layer, and an upper insulating layer formed on an upper surface of the first metal silicide layer. And a second sidewall insulating layer formed on side surfaces of the first sidewall insulating layer and the upper insulating layer. 5. A method for manufacturing a semiconductor device, comprising the following steps (a) to (h). (A) forming a conductive layer containing silicon in a predetermined region on a main surface of a silicon substrate via an insulating layer; (b) forming a first sidewall insulating layer on a side surface of the conductive layer; A) forming an impurity diffusion layer on a surface of the main surface of the silicon substrate; (d) forming a metal silicide layer on the surface of the conductive layer and the impurity diffusion layer in a self-aligned manner; Forming an insulating layer covering a surface of the metal silicide layer on the conductive layer and the conductive layer, and electrically insulating the conductive layer and the metal silicide layer; (f) forming an interlayer insulating layer;
(G) using the first sidewall insulating layer and the insulating layer as a mask, forming a contact hole in a self-aligned manner with at least a part of the impurity diffusion layer exposed; and (h) forming a contact hole in the contact hole. Forming a wiring layer on the substrate. 6. The method according to claim 5, wherein the conductive layer is a gate electrode layer including a gate electrode. 7. The method according to claim 5, wherein at least a part of the conductive layer is a wiring layer existing on an element isolation region. 8. The method according to claim 5, wherein the insulating layer formed in the step (e) comprises: forming an upper insulating layer on an upper surface of the metal silicide layer on the conductive layer; A method of manufacturing a semiconductor device obtained by forming a second sidewall insulating layer on a side face of a first sidewall insulating layer and the upper insulating layer. 9. The method according to claim 8, wherein the insulating layer is formed at a temperature of 800 ° C. or lower.