ATE6892T1 - Programmierbare speicher/logik-matrix. - Google Patents

Programmierbare speicher/logik-matrix.

Info

Publication number
ATE6892T1
ATE6892T1 AT79901588T AT79901588T ATE6892T1 AT E6892 T1 ATE6892 T1 AT E6892T1 AT 79901588 T AT79901588 T AT 79901588T AT 79901588 T AT79901588 T AT 79901588T AT E6892 T1 ATE6892 T1 AT E6892T1
Authority
AT
Austria
Prior art keywords
subset
row
conductors
column
coupled
Prior art date
Application number
AT79901588T
Other languages
German (de)
English (en)
Inventor
Suhas S. Patil
Original Assignee
Massachusetts Institute Of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massachusetts Institute Of Technology filed Critical Massachusetts Institute Of Technology
Application granted granted Critical
Publication of ATE6892T1 publication Critical patent/ATE6892T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT79901588T 1978-11-01 1979-10-26 Programmierbare speicher/logik-matrix. ATE6892T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/956,794 US4293783A (en) 1978-11-01 1978-11-01 Storage/logic array

Publications (1)

Publication Number Publication Date
ATE6892T1 true ATE6892T1 (de) 1984-04-15

Family

ID=25498706

Family Applications (1)

Application Number Title Priority Date Filing Date
AT79901588T ATE6892T1 (de) 1978-11-01 1979-10-26 Programmierbare speicher/logik-matrix.

Country Status (6)

Country Link
US (1) US4293783A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0020608B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH0516054B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AT (1) ATE6892T1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2966856D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1980001029A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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US5253363A (en) * 1988-03-15 1993-10-12 Edward Hyman Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array
US5377123A (en) * 1992-06-08 1994-12-27 Hyman; Edward Programmable logic device
US5644497A (en) * 1988-03-15 1997-07-01 Hyman; Edward Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array
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US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5021689A (en) * 1989-01-19 1991-06-04 National Semiconductor Corp. Multiple page programmable logic architecture
US4942319A (en) * 1989-01-19 1990-07-17 National Semiconductor Corp. Multiple page programmable logic architecture
US5099150A (en) * 1989-09-29 1992-03-24 Sgs-Thomson Microelectronics, Inc. Circuit block for programmable logic devices, configurable as a user-writable memory or a logic circuit
US4975601A (en) * 1989-09-29 1990-12-04 Sgs-Thomson Microelectronics, Inc. User-writable random access memory logic block for programmable logic devices
US5128559A (en) * 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
US5055712A (en) * 1990-04-05 1991-10-08 National Semiconductor Corp. Register file with programmable control, decode and/or data manipulation
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
DE69131679T2 (de) * 1990-07-30 2000-05-11 Texas Instruments Inc., Dallas Statisches Speicherfeld mit wahlfreiem Zugriff, welches mindestens eine arithmetisch-logische Einheit enthält
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US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
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US20020130681A1 (en) * 1991-09-03 2002-09-19 Cliff Richard G. Programmable logic array integrated circuits
US5367209A (en) * 1992-01-07 1994-11-22 Hauck Scott A Field programmable gate array for synchronous and asynchronous operation
US5319261A (en) * 1992-07-30 1994-06-07 Aptix Corporation Reprogrammable interconnect architecture using fewer storage cells than switches
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US6049223A (en) 1995-03-22 2000-04-11 Altera Corporation Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US5757207A (en) * 1995-03-22 1998-05-26 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US5977791A (en) 1996-04-15 1999-11-02 Altera Corporation Embedded memory block with FIFO mode for programmable logic device
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US6034857A (en) 1997-07-16 2000-03-07 Altera Corporation Input/output buffer with overcurrent protection circuit
US6020760A (en) 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6011744A (en) * 1997-07-16 2000-01-04 Altera Corporation Programmable logic device with multi-port memory
US6467017B1 (en) 1998-06-23 2002-10-15 Altera Corporation Programmable logic device having embedded dual-port random access memory configurable as single-port memory
US6262933B1 (en) 1999-01-29 2001-07-17 Altera Corporation High speed programmable address decoder
JP2000334994A (ja) * 1999-05-27 2000-12-05 Futaba Corp 蛍光発光装置
GB2351824B (en) 1999-07-02 2004-03-31 Altera Corp Embedded memory blocks for programmable logic
US6720796B1 (en) 2001-05-06 2004-04-13 Altera Corporation Multiple size memories in a programmable logic device
US7111110B1 (en) 2002-12-10 2006-09-19 Altera Corporation Versatile RAM for programmable logic device
US20040186639A1 (en) * 2003-03-21 2004-09-23 Volvo Trucks North America, Inc. Programmable multi-function switch and display
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8874607B2 (en) * 2010-08-17 2014-10-28 Fujitsu Limited Representing sensor data as binary decision diagrams
US9138143B2 (en) 2010-08-17 2015-09-22 Fujitsu Limited Annotating medical data represented by characteristic functions
US8930394B2 (en) * 2010-08-17 2015-01-06 Fujitsu Limited Querying sensor data stored as binary decision diagrams
US9002781B2 (en) 2010-08-17 2015-04-07 Fujitsu Limited Annotating environmental data represented by characteristic functions
US9176819B2 (en) 2011-09-23 2015-11-03 Fujitsu Limited Detecting sensor malfunctions using compression analysis of binary decision diagrams
US9075908B2 (en) 2011-09-23 2015-07-07 Fujitsu Limited Partitioning medical binary decision diagrams for size optimization
US10884663B2 (en) 2019-03-14 2021-01-05 Western Digital Technologies, Inc. Executable memory cells

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Also Published As

Publication number Publication date
US4293783A (en) 1981-10-06
JPH0516054B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-03-03
EP0020608A4 (en) 1981-03-24
WO1980001029A1 (en) 1980-05-15
DE2966856D1 (en) 1984-05-03
JPS55501003A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1980-11-20
EP0020608B1 (en) 1984-03-28
EP0020608A1 (en) 1981-01-07

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