ATE551720T1 - Weiterverteilungsschicht für die waferebenen- kapselung auf chipmassstab und verfahren dafür - Google Patents

Weiterverteilungsschicht für die waferebenen- kapselung auf chipmassstab und verfahren dafür

Info

Publication number
ATE551720T1
ATE551720T1 AT06809636T AT06809636T ATE551720T1 AT E551720 T1 ATE551720 T1 AT E551720T1 AT 06809636 T AT06809636 T AT 06809636T AT 06809636 T AT06809636 T AT 06809636T AT E551720 T1 ATE551720 T1 AT E551720T1
Authority
AT
Austria
Prior art keywords
layer
bump
metal
bond pad
pad
Prior art date
Application number
AT06809636T
Other languages
English (en)
Inventor
Michael Loo
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE551720T1 publication Critical patent/ATE551720T1/de

Links

Classifications

    • H10W20/49—
    • H10W70/60—
    • H10W72/012—
    • H10W72/019—
    • H10W72/244—
    • H10W72/252—
    • H10W72/29—
    • H10W72/9223—
    • H10W72/923—
    • H10W72/942—
    • H10W74/129—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
AT06809636T 2005-10-19 2006-10-18 Weiterverteilungsschicht für die waferebenen- kapselung auf chipmassstab und verfahren dafür ATE551720T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72855305P 2005-10-19 2005-10-19
PCT/IB2006/053840 WO2007046062A2 (en) 2005-10-19 2006-10-18 Redistribution layer for wafer-level chip scale package and method therefor

Publications (1)

Publication Number Publication Date
ATE551720T1 true ATE551720T1 (de) 2012-04-15

Family

ID=37847297

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06809636T ATE551720T1 (de) 2005-10-19 2006-10-18 Weiterverteilungsschicht für die waferebenen- kapselung auf chipmassstab und verfahren dafür

Country Status (7)

Country Link
US (1) US7709954B2 (de)
EP (1) EP1941541B1 (de)
JP (1) JP2009513013A (de)
CN (1) CN100587931C (de)
AT (1) ATE551720T1 (de)
TW (1) TW200733270A (de)
WO (1) WO2007046062A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090294971A1 (en) * 2008-06-02 2009-12-03 International Business Machines Corporation Electroless nickel leveling of lga pad sites for high performance organic lga
CN101870443A (zh) * 2009-04-22 2010-10-27 昆山西钛微电子科技有限公司 多层线路导通型晶圆级微机电系统芯片
JP5355504B2 (ja) * 2009-07-30 2013-11-27 株式会社東芝 半導体装置の製造方法および半導体装置
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8659170B2 (en) * 2010-01-20 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
CN102431963B (zh) * 2011-12-15 2015-04-01 中国科学院上海微系统与信息技术研究所 低温下砷化镓图像传感器圆片级芯片尺寸封装工艺
TWI490994B (zh) * 2012-09-03 2015-07-01 矽品精密工業股份有限公司 半導體封裝件中之連接結構
KR101936039B1 (ko) 2012-10-30 2019-01-08 삼성전자 주식회사 반도체 장치
CN104617069A (zh) * 2014-12-19 2015-05-13 南通富士通微电子股份有限公司 半导体圆片级封装结构
US20170323863A1 (en) * 2016-05-09 2017-11-09 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
CN108573980B (zh) * 2017-03-09 2021-02-19 群创光电股份有限公司 导体结构以及面板装置
US10420211B2 (en) * 2017-08-09 2019-09-17 Advanced Semiconductor Engineering, Inc. Semiconductor package device
CN108336052B (zh) * 2018-02-08 2021-01-05 颀中科技（苏州）有限公司 金属再布线结构、芯片封装器件及芯片封装器件制作工艺
DE102018124497B4 (de) 2018-10-04 2022-06-30 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zum Bilden einer Halbleitervorrichtung
DE102019125447A1 (de) * 2019-09-20 2021-03-25 Infineon Technologies Ag Halbleitersubstrat mit einem Bondpat-Material auf Aluminiumbasis
CN113471061B (zh) * 2021-06-30 2024-07-16 颀中科技（苏州）有限公司 晶圆表面介电层的制备方法、晶圆结构及凸块的成型方法
TWI903314B (zh) * 2022-12-16 2025-11-01 銓心半導體異質整合股份有限公司 半導體封裝及用於製造半導體封裝之方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6521970B1 (en) * 2000-09-01 2003-02-18 National Semiconductor Corporation Chip scale package with compliant leads
TW449813B (en) * 2000-10-13 2001-08-11 Advanced Semiconductor Eng Semiconductor device with bump electrode
CN1452217A (zh) * 2002-04-15 2003-10-29 裕沛科技股份有限公司 晶圆型态封装及其制作方法
JP2004055628A (ja) * 2002-07-17 2004-02-19 Dainippon Printing Co Ltd ウエハレベルの半導体装置及びその作製方法
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
TWI223882B (en) * 2003-06-30 2004-11-11 Advanced Semiconductor Eng Bumping process

Also Published As

Publication number Publication date
WO2007046062A2 (en) 2007-04-26
WO2007046062A3 (en) 2007-07-05
CN100587931C (zh) 2010-02-03
JP2009513013A (ja) 2009-03-26
US20090072397A1 (en) 2009-03-19
TW200733270A (en) 2007-09-01
CN101292335A (zh) 2008-10-22
US7709954B2 (en) 2010-05-04
EP1941541A2 (de) 2008-07-09
EP1941541B1 (de) 2012-03-28

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