ATE534998T1 - Verfahren und system zur bereitstellung von nahtloser selbstaktualisierung für gezielte bankaktualisierung bei flüchtigen speichern - Google Patents

Verfahren und system zur bereitstellung von nahtloser selbstaktualisierung für gezielte bankaktualisierung bei flüchtigen speichern

Info

Publication number
ATE534998T1
ATE534998T1 AT05760239T AT05760239T ATE534998T1 AT E534998 T1 ATE534998 T1 AT E534998T1 AT 05760239 T AT05760239 T AT 05760239T AT 05760239 T AT05760239 T AT 05760239T AT E534998 T1 ATE534998 T1 AT E534998T1
Authority
AT
Austria
Prior art keywords
volatile memory
self
refresh mode
update
memory
Prior art date
Application number
AT05760239T
Other languages
German (de)
English (en)
Inventor
Perry Willmann Remaklus Jr
Robert Michael Walker
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE534998T1 publication Critical patent/ATE534998T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT05760239T 2004-05-27 2005-05-26 Verfahren und system zur bereitstellung von nahtloser selbstaktualisierung für gezielte bankaktualisierung bei flüchtigen speichern ATE534998T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US57533504P 2004-05-27 2004-05-27
US10/982,277 US7088633B2 (en) 2004-05-27 2004-11-05 Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
PCT/US2005/018917 WO2005119692A1 (en) 2004-05-27 2005-05-26 Method and system for providing seamless self-refresh for directed bank refresh in volatile memories

Publications (1)

Publication Number Publication Date
ATE534998T1 true ATE534998T1 (de) 2011-12-15

Family

ID=34972468

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05760239T ATE534998T1 (de) 2004-05-27 2005-05-26 Verfahren und system zur bereitstellung von nahtloser selbstaktualisierung für gezielte bankaktualisierung bei flüchtigen speichern

Country Status (9)

Country Link
US (1) US7088633B2 (cg-RX-API-DMAC7.html)
EP (1) EP1751769B1 (cg-RX-API-DMAC7.html)
JP (2) JP2008500680A (cg-RX-API-DMAC7.html)
KR (1) KR100843529B1 (cg-RX-API-DMAC7.html)
CN (1) CN1977340B (cg-RX-API-DMAC7.html)
AT (1) ATE534998T1 (cg-RX-API-DMAC7.html)
IL (1) IL179460A0 (cg-RX-API-DMAC7.html)
MX (1) MXPA06013788A (cg-RX-API-DMAC7.html)
WO (1) WO2005119692A1 (cg-RX-API-DMAC7.html)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7079440B2 (en) * 2004-05-27 2006-07-18 Qualcomm Incorporated Method and system for providing directed bank refresh for volatile memories
US7184350B2 (en) * 2004-05-27 2007-02-27 Qualcomm Incorporated Method and system for providing independent bank refresh for volatile memories
US7953921B2 (en) * 2004-12-28 2011-05-31 Qualcomm Incorporated Directed auto-refresh synchronization
KR100665901B1 (ko) * 2005-03-31 2007-01-11 주식회사 하이닉스반도체 반도체 기억 소자의 개별 뱅크 리프레쉬 회로 및 방법
KR100838375B1 (ko) * 2006-04-28 2008-06-13 주식회사 하이닉스반도체 반도체 메모리 장치
JP4813264B2 (ja) * 2006-06-14 2011-11-09 株式会社日立製作所 ストレージシステム
KR100748460B1 (ko) * 2006-08-16 2007-08-13 주식회사 하이닉스반도체 반도체 메모리 및 그 제어방법
KR100802074B1 (ko) 2006-09-08 2008-02-12 주식회사 하이닉스반도체 리프레쉬명령 생성회로를 포함하는 메모리장치 및리프레쉬명령 생성방법.
US7922509B2 (en) * 2007-06-15 2011-04-12 Tyco Electronics Corporation Surface mount electrical connector having insulated pin
US7590021B2 (en) * 2007-07-26 2009-09-15 Qualcomm Incorporated System and method to reduce dynamic RAM power consumption via the use of valid data indicators
US7990795B2 (en) 2009-02-19 2011-08-02 Freescale Semiconductor, Inc. Dynamic random access memory (DRAM) refresh
WO2010123681A2 (en) 2009-04-22 2010-10-28 Rambus Inc. Protocol for refresh between a memory controller and a memory device
US8310893B2 (en) * 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US9053812B2 (en) 2010-09-24 2015-06-09 Intel Corporation Fast exit from DRAM self-refresh
US9292426B2 (en) 2010-09-24 2016-03-22 Intel Corporation Fast exit from DRAM self-refresh
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
KR20150015560A (ko) * 2013-07-30 2015-02-11 에스케이하이닉스 주식회사 반도체장치를 포함하는 반도체시스템
JP2015076110A (ja) * 2013-10-08 2015-04-20 マイクロン テクノロジー， インク． 半導体装置及びこれを備えるデータ処理システム
KR102163983B1 (ko) * 2013-11-07 2020-10-12 에스케이하이닉스 주식회사 반도체 메모리 장치
KR20160023274A (ko) * 2014-08-22 2016-03-03 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
US10331526B2 (en) * 2015-07-31 2019-06-25 Qualcomm Incorporated Systems, methods, and apparatus for frequency reset of a memory
US9875785B2 (en) * 2015-10-01 2018-01-23 Qualcomm Incorporated Refresh timer synchronization between memory controller and memory
US11079945B2 (en) * 2018-09-20 2021-08-03 Ati Technologies Ulc Dynamic configuration of memory timing parameters

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687107A (en) * 1985-05-02 1987-08-18 Pennwalt Corporation Apparatus for sizing and sorting articles
JPH1166843A (ja) * 1997-08-08 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
WO1999046775A2 (en) 1998-03-10 1999-09-16 Rambus, Inc. Performing concurrent refresh and current control operations in a memory subsystem
JP2001332083A (ja) * 2000-05-18 2001-11-30 Nec Corp 半導体記憶装置およびそのアドレス制御方法
US6665224B1 (en) 2002-05-22 2003-12-16 Infineon Technologies Ag Partial refresh for synchronous dynamic random access memory (SDRAM) circuits
US7236416B2 (en) * 2004-05-21 2007-06-26 Qualcomm Incorporated Method and system for controlling refresh in volatile memories
US7184350B2 (en) * 2004-05-27 2007-02-27 Qualcomm Incorporated Method and system for providing independent bank refresh for volatile memories
US7079440B2 (en) * 2004-05-27 2006-07-18 Qualcomm Incorporated Method and system for providing directed bank refresh for volatile memories

Also Published As

Publication number Publication date
EP1751769A1 (en) 2007-02-14
JP2012014824A (ja) 2012-01-19
JP2008500680A (ja) 2008-01-10
US7088633B2 (en) 2006-08-08
CN1977340A (zh) 2007-06-06
KR100843529B1 (ko) 2008-07-03
US20050265103A1 (en) 2005-12-01
IL179460A0 (en) 2007-05-15
MXPA06013788A (es) 2007-03-01
WO2005119692A1 (en) 2005-12-15
KR20070027630A (ko) 2007-03-09
EP1751769B1 (en) 2011-11-23
CN1977340B (zh) 2012-05-09

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