ATE532264T1 - Interne lastübertragung für schaltkreise - Google Patents

Interne lastübertragung für schaltkreise

Info

Publication number
ATE532264T1
ATE532264T1 AT09782812T AT09782812T ATE532264T1 AT E532264 T1 ATE532264 T1 AT E532264T1 AT 09782812 T AT09782812 T AT 09782812T AT 09782812 T AT09782812 T AT 09782812T AT E532264 T1 ATE532264 T1 AT E532264T1
Authority
AT
Austria
Prior art keywords
sleep
fast
circuits
circuit
load transfer
Prior art date
Application number
AT09782812T
Other languages
English (en)
Inventor
Moon Kim
Daeik Kim
Choongyeun Cho
Elmer Corbin
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE532264T1 publication Critical patent/ATE532264T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
AT09782812T 2008-11-21 2009-09-09 Interne lastübertragung für schaltkreise ATE532264T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/275,521 US7804329B2 (en) 2008-11-21 2008-11-21 Internal charge transfer for circuits
PCT/EP2009/061686 WO2010057694A1 (en) 2008-11-21 2009-09-09 Internal charge transfer for circuits

Publications (1)

Publication Number Publication Date
ATE532264T1 true ATE532264T1 (de) 2011-11-15

Family

ID=41394414

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09782812T ATE532264T1 (de) 2008-11-21 2009-09-09 Interne lastübertragung für schaltkreise

Country Status (8)

Country Link
US (1) US7804329B2 (de)
EP (1) EP2297854B1 (de)
JP (1) JP5363586B2 (de)
KR (1) KR20110091006A (de)
CN (1) CN102224677B (de)
AT (1) ATE532264T1 (de)
TW (1) TW201033801A (de)
WO (1) WO2010057694A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9886389B2 (en) 2008-11-21 2018-02-06 International Business Machines Corporation Cache memory bypass in a multi-core processor (MCP)
US9824008B2 (en) 2008-11-21 2017-11-21 International Business Machines Corporation Cache memory sharing in a multi-core processor (MCP)
US8566620B2 (en) * 2010-07-29 2013-10-22 Freescale Semiconductor, Inc. Data processing having multiple low power modes and method therefor

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Also Published As

Publication number Publication date
CN102224677B (zh) 2014-05-21
US20100127730A1 (en) 2010-05-27
JP2012509629A (ja) 2012-04-19
KR20110091006A (ko) 2011-08-10
TW201033801A (en) 2010-09-16
EP2297854B1 (de) 2011-11-02
EP2297854A1 (de) 2011-03-23
WO2010057694A1 (en) 2010-05-27
US7804329B2 (en) 2010-09-28
JP5363586B2 (ja) 2013-12-11
CN102224677A (zh) 2011-10-19

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