ATE525820T1 - Verfahren und vorrichtung zur leitungslatenzmessung in transportnetzwerken - Google Patents

Verfahren und vorrichtung zur leitungslatenzmessung in transportnetzwerken

Info

Publication number
ATE525820T1
ATE525820T1 AT09305624T AT09305624T ATE525820T1 AT E525820 T1 ATE525820 T1 AT E525820T1 AT 09305624 T AT09305624 T AT 09305624T AT 09305624 T AT09305624 T AT 09305624T AT E525820 T1 ATE525820 T1 AT E525820T1
Authority
AT
Austria
Prior art keywords
network node
latency
virtual concatenation
members
measuring line
Prior art date
Application number
AT09305624T
Other languages
English (en)
Inventor
Stefan Ansorge
Siegfried Beilharz
Original Assignee
Alcatel Lucent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Lucent filed Critical Alcatel Lucent
Application granted granted Critical
Publication of ATE525820T1 publication Critical patent/ATE525820T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0893—Assignment of logical groups to network elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0094—Virtual Concatenation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Environmental & Geological Engineering (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
AT09305624T 2009-06-30 2009-06-30 Verfahren und vorrichtung zur leitungslatenzmessung in transportnetzwerken ATE525820T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP09305624A EP2278738B1 (de) 2009-06-30 2009-06-30 Verfahren und Vorrichtung zur Leitungslatenzmessung in Transportnetzwerken

Publications (1)

Publication Number Publication Date
ATE525820T1 true ATE525820T1 (de) 2011-10-15

Family

ID=41258921

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09305624T ATE525820T1 (de) 2009-06-30 2009-06-30 Verfahren und vorrichtung zur leitungslatenzmessung in transportnetzwerken

Country Status (7)

Country Link
US (1) US20120087252A1 (de)
EP (1) EP2278738B1 (de)
JP (1) JP2012531862A (de)
KR (1) KR20120032545A (de)
CN (1) CN102474373A (de)
AT (1) ATE525820T1 (de)
WO (1) WO2011000625A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101718374B1 (ko) * 2013-01-11 2017-03-21 후아웨이 테크놀러지 컴퍼니 리미티드 네트워크 장치에 대한 네트워크 기능 가상화
TWI528755B (zh) 2013-12-06 2016-04-01 財團法人工業技術研究院 軟體定義網路中用於延遲量測之網路控制器、延遲量測系統及延遲量測方法
CA3005164A1 (en) * 2015-12-10 2017-06-15 Sony Corporation Receiving apparatus and data processing method for delay compensation
US10193765B2 (en) * 2016-05-19 2019-01-29 Ciena Corporation Protection switching systems and methods in a packet network based on signal degrade
CN110417503B (zh) * 2019-07-31 2021-03-05 锐捷网络股份有限公司 一种用于测试时钟网络延时的方法及数字通信设备
US11604751B1 (en) * 2021-05-10 2023-03-14 Xilinx, Inc. Optimizing hardware design throughput by latency aware balancing of re-convergent paths

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781597A (en) * 1995-02-16 1998-07-14 Alcatel Sel Aktiengesellschaft Synchronous digital transmission system having justification circuit that counts frame bytes, calculates offsets, compares thresholds, and initiates justification action
JP2751883B2 (ja) * 1995-08-15 1998-05-18 日本電気株式会社 局間伝送遅延時間測定方法
US6545979B1 (en) * 1998-11-27 2003-04-08 Alcatel Canada Inc. Round trip delay measurement
JP2000332715A (ja) * 1999-05-19 2000-11-30 Nec Corp Ｓｄｈ伝送のノード間距離測定システム及び方法
JP3479248B2 (ja) * 1999-12-17 2003-12-15 日本電気株式会社 Ａｔｍ伝送試験装置
JP2002374301A (ja) * 2001-06-14 2002-12-26 Hitachi Ltd 通信品質測定サービスおよび装置
GB0200918D0 (en) * 2002-01-16 2002-03-06 Agilent Technologies Inc Method and apparatus for measuring diffential delay
IL152314A (en) * 2002-10-16 2007-07-04 Eci Telecom Ltd Handling traffic in a synchronous communication network
KR100532299B1 (ko) * 2003-01-30 2005-11-29 삼성전자주식회사 광선로로 접속되는 주 기지국과 원격 기지국간의 지연측정 및 보상장치
JP4390568B2 (ja) * 2004-01-19 2009-12-24 富士通株式会社 遅延測定システム
US8289859B2 (en) * 2004-05-25 2012-10-16 Alcatel Lucent Link delay determination using virtual concatenation
JP4966779B2 (ja) * 2007-07-27 2012-07-04 富士通株式会社 ネットワーク遅延計測方法及び通信システム
JP2010141683A (ja) * 2008-12-12 2010-06-24 Mitsubishi Electric Corp 光伝送装置及び分散補償器
US8774232B2 (en) * 2010-01-08 2014-07-08 Ciena Corporation Systems and methods of measuring latency and routing thereon in optical networks

Also Published As

Publication number Publication date
JP2012531862A (ja) 2012-12-10
KR20120032545A (ko) 2012-04-05
US20120087252A1 (en) 2012-04-12
CN102474373A (zh) 2012-05-23
EP2278738A1 (de) 2011-01-26
WO2011000625A1 (en) 2011-01-06
EP2278738B1 (de) 2011-09-21

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