ATE518248T1 - Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gate - Google Patents

Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gate

Info

Publication number
ATE518248T1
ATE518248T1 AT04710959T AT04710959T ATE518248T1 AT E518248 T1 ATE518248 T1 AT E518248T1 AT 04710959 T AT04710959 T AT 04710959T AT 04710959 T AT04710959 T AT 04710959T AT E518248 T1 ATE518248 T1 AT E518248T1
Authority
AT
Austria
Prior art keywords
stack
layer
gate layer
producing
memory cell
Prior art date
Application number
AT04710959T
Other languages
English (en)
Inventor
Duuren Michiel Van
Schaijk Robertus Van
Youri Ponomarev
Jacob Hooker
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE518248T1 publication Critical patent/ATE518248T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AT04710959T 2003-02-26 2004-02-13 Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gate ATE518248T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100469 2003-02-26
PCT/IB2004/050113 WO2004077498A2 (en) 2003-02-26 2004-02-13 Method of manufacturing a non-volatile memory cell with a lateral select gate

Publications (1)

Publication Number Publication Date
ATE518248T1 true ATE518248T1 (de) 2011-08-15

Family

ID=32921606

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04710959T ATE518248T1 (de) 2003-02-26 2004-02-13 Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gate

Country Status (5)

Country Link
US (1) US7429513B2 (de)
EP (1) EP1599908B1 (de)
JP (1) JP2006519491A (de)
AT (1) ATE518248T1 (de)
WO (1) WO2004077498A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7595528B2 (en) * 2004-03-10 2009-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7816726B2 (en) 2007-12-20 2010-10-19 Promos Technologies Pte. Ltd. Nonvolatile memories with laterally recessed charge-trapping dielectric
KR101010437B1 (ko) 2008-07-15 2011-01-21 주식회사 동부하이텍 플래시 메모리 소자 및 그 제조 방법
US20100163952A1 (en) * 2008-12-31 2010-07-01 Chia-Hong Jan Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate
US8470670B2 (en) * 2009-09-23 2013-06-25 Infineon Technologies Ag Method for making semiconductor device
US8101492B2 (en) * 2009-09-23 2012-01-24 Infineon Technologies Ag Method for making semiconductor device
US8822329B2 (en) * 2009-09-28 2014-09-02 Infineon Technologies Ag Method for making conductive interconnects
US8101477B1 (en) 2010-09-28 2012-01-24 Infineon Technologies Ag Method for making semiconductor device
US9318336B2 (en) * 2011-10-27 2016-04-19 Globalfoundries U.S. 2 Llc Non-volatile memory structure employing high-k gate dielectric and metal gate
US8951864B2 (en) * 2012-02-13 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Split-gate device and method of fabricating the same
US9368644B2 (en) 2013-12-20 2016-06-14 Cypress Semiconductor Corporation Gate formation memory by planarization
JP6343721B2 (ja) * 2015-01-23 2018-06-13 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 金属ゲートを備えた自己整合型分割ゲートメモリセルアレイ及び論理デバイスの形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
KR0172273B1 (ko) * 1995-06-24 1999-02-01 김주용 플래쉬 메모리 셀의 제조방법
US6261903B1 (en) * 1998-05-14 2001-07-17 Mosel Vitelic, Inc. Floating gate method and device
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US6432773B1 (en) * 1999-04-08 2002-08-13 Microchip Technology Incorporated Memory cell having an ONO film with an ONO sidewall and method of fabricating same
US6642103B2 (en) * 2000-03-08 2003-11-04 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing the same
US6562681B2 (en) * 2001-06-13 2003-05-13 Mosel Vitelic, Inc. Nonvolatile memories with floating gate spacers, and methods of fabrication

Also Published As

Publication number Publication date
US20060166420A1 (en) 2006-07-27
EP1599908B1 (de) 2011-07-27
WO2004077498A2 (en) 2004-09-10
WO2004077498A3 (en) 2004-11-04
US7429513B2 (en) 2008-09-30
EP1599908A2 (de) 2005-11-30
JP2006519491A (ja) 2006-08-24

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