ATE517416T1 - Speicherbusausgangstreiber einer mehrbank- speicheranordnung und verfahren dafür - Google Patents

Speicherbusausgangstreiber einer mehrbank- speicheranordnung und verfahren dafür

Info

Publication number
ATE517416T1
ATE517416T1 AT07863608T AT07863608T ATE517416T1 AT E517416 T1 ATE517416 T1 AT E517416T1 AT 07863608 T AT07863608 T AT 07863608T AT 07863608 T AT07863608 T AT 07863608T AT E517416 T1 ATE517416 T1 AT E517416T1
Authority
AT
Austria
Prior art keywords
output driver
bus
bus output
tri
memory
Prior art date
Application number
AT07863608T
Other languages
English (en)
Inventor
Jentsung Lin
Ajay Anant Ingle
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE517416T1 publication Critical patent/ATE517416T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
AT07863608T 2006-10-30 2007-10-29 Speicherbusausgangstreiber einer mehrbank- speicheranordnung und verfahren dafür ATE517416T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/554,522 US7505342B2 (en) 2006-10-30 2006-10-30 Memory bus output driver of a multi-bank memory device and method therefor
PCT/US2007/082824 WO2008055099A2 (en) 2006-10-30 2007-10-29 Memory bus output driver of a multi-bank memory device and method therefor

Publications (1)

Publication Number Publication Date
ATE517416T1 true ATE517416T1 (de) 2011-08-15

Family

ID=39323757

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07863608T ATE517416T1 (de) 2006-10-30 2007-10-29 Speicherbusausgangstreiber einer mehrbank- speicheranordnung und verfahren dafür

Country Status (7)

Country Link
US (1) US7505342B2 (de)
EP (1) EP2082399B1 (de)
JP (3) JP2010508618A (de)
KR (1) KR101059270B1 (de)
CN (1) CN101529520B (de)
AT (1) ATE517416T1 (de)
WO (1) WO2008055099A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8570827B2 (en) * 2010-12-20 2013-10-29 Apple Inc. Physical organization of memory to reduce power consumption
US8767493B2 (en) * 2011-06-27 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM differential voltage sensing apparatus
US9390033B2 (en) 2013-11-13 2016-07-12 Sandisk Technologies Llc Method and system for communicating with non-volatile memory via multiple data paths
US9377968B2 (en) 2013-11-13 2016-06-28 Sandisk Technologies Llc Method and system for using templates to communicate with non-volatile memory
US9430411B2 (en) 2013-11-13 2016-08-30 Sandisk Technologies Llc Method and system for communicating with non-volatile memory
US10140044B2 (en) * 2016-03-31 2018-11-27 Qualcomm Incorporated Efficient memory bank design
US10043557B1 (en) * 2017-10-10 2018-08-07 Micron Technology, Inc. Apparatuses and methods for parallel I/O operations in a memory

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
JPS57198594A (en) * 1981-06-01 1982-12-06 Hitachi Ltd Semiconductor storage device
JPS63200391A (ja) * 1987-02-16 1988-08-18 Toshiba Corp スタテイツク型半導体メモリ
JPH023165A (ja) * 1988-06-20 1990-01-08 Hitachi Ltd 半導体記憶装置
JPH02244479A (ja) * 1989-03-16 1990-09-28 Fujitsu Ltd 半導体メモリ装置
JP2717712B2 (ja) * 1989-08-18 1998-02-25 三菱電機株式会社 半導体記憶装置
JP2938706B2 (ja) * 1992-04-27 1999-08-25 三菱電機株式会社 同期型半導体記憶装置
GB9502646D0 (en) * 1995-02-10 1995-03-29 Texas Instruments Ltd Bus maintenance circuit
DE69631284D1 (de) * 1996-03-29 2004-02-12 St Microelectronics Srl Programmier- und Lese-Verwaltungsarchitektur für Speicheranordnungen, insbesondere für Testzwecke
US5680365A (en) * 1996-05-16 1997-10-21 Mitsubishi Semiconductor America, Inc. Shared dram I/O databus for high speed operation
US6163863A (en) * 1998-05-22 2000-12-19 Micron Technology, Inc. Method and circuit for compressing test data in a memory device
JP2000021168A (ja) * 1998-06-30 2000-01-21 Fujitsu Ltd 半導体メモリ及びこれを備えた半導体装置
US6378008B1 (en) * 1998-11-25 2002-04-23 Cypress Semiconductor Corporation Output data path scheme in a memory device
JP3784979B2 (ja) * 1999-02-09 2006-06-14 株式会社東芝 バス駆動回路
JP2001043671A (ja) * 1999-07-28 2001-02-16 Oki Micro Design Co Ltd 半導体装置
US6487688B1 (en) * 1999-12-23 2002-11-26 Logicvision, Inc. Method for testing circuits with tri-state drivers and circuit for use therewith
JP2002093159A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
US7234089B2 (en) * 2001-10-27 2007-06-19 Stmicroelectronics Limited Tristate buses
US6642749B1 (en) * 2002-09-27 2003-11-04 Lsi Logic Corporation Latching sense amplifier with tri-state output
US6822439B2 (en) * 2003-01-30 2004-11-23 Broadcom Corporation Control of tristate buses during scan test
US7280401B2 (en) * 2003-07-10 2007-10-09 Telairity Semiconductor, Inc. High speed data access memory arrays

Also Published As

Publication number Publication date
CN101529520A (zh) 2009-09-09
WO2008055099A2 (en) 2008-05-08
JP2013093094A (ja) 2013-05-16
WO2008055099A3 (en) 2008-12-04
US20080112243A1 (en) 2008-05-15
KR20090077848A (ko) 2009-07-15
EP2082399B1 (de) 2011-07-20
JP5563056B2 (ja) 2014-07-30
JP5797813B2 (ja) 2015-10-21
CN101529520B (zh) 2013-04-03
KR101059270B1 (ko) 2011-08-24
EP2082399A2 (de) 2009-07-29
JP2010508618A (ja) 2010-03-18
US7505342B2 (en) 2009-03-17
JP2014222556A (ja) 2014-11-27

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