ATE504941T1 - Prozess zum verbessern der oberflächenrauigkeit eines halbleiterwafers - Google Patents

Prozess zum verbessern der oberflächenrauigkeit eines halbleiterwafers

Info

Publication number
ATE504941T1
ATE504941T1 AT03819093T AT03819093T ATE504941T1 AT E504941 T1 ATE504941 T1 AT E504941T1 AT 03819093 T AT03819093 T AT 03819093T AT 03819093 T AT03819093 T AT 03819093T AT E504941 T1 ATE504941 T1 AT E504941T1
Authority
AT
Austria
Prior art keywords
semiconductor wafer
improving
surface roughness
wafer
carried out
Prior art date
Application number
AT03819093T
Other languages
English (en)
Inventor
Eric Neyret
Christophe Maleville
Ludovic Ecarnot
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE504941T1 publication Critical patent/ATE504941T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AT03819093T 2003-12-03 2003-12-03 Prozess zum verbessern der oberflächenrauigkeit eines halbleiterwafers ATE504941T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2003/006351 WO2005055307A1 (en) 2003-12-03 2003-12-03 Process for improving the surface roughness of a semiconductor wafer

Publications (1)

Publication Number Publication Date
ATE504941T1 true ATE504941T1 (de) 2011-04-15

Family

ID=34640308

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03819093T ATE504941T1 (de) 2003-12-03 2003-12-03 Prozess zum verbessern der oberflächenrauigkeit eines halbleiterwafers

Country Status (7)

Country Link
EP (1) EP1697981B9 (de)
JP (1) JP4694372B2 (de)
CN (1) CN1879205B (de)
AT (1) ATE504941T1 (de)
AU (1) AU2003296844A1 (de)
DE (1) DE60336687D1 (de)
WO (1) WO2005055307A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005055308A1 (en) * 2003-12-03 2005-06-16 S.O.I.Tec Silicon On Insulator Technologies Process for improving the surface roughness of a wafer
CN104550133B (zh) * 2014-12-11 2017-02-22 河北同光晶体有限公司 一种去除碳化硅单晶中空微缺陷内部、及晶片表面有机污染物的方法
CN106920746A (zh) * 2015-12-25 2017-07-04 有研半导体材料有限公司 一种改善硅片表面微缺陷的方法
JP6927143B2 (ja) * 2018-05-17 2021-08-25 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US10381218B1 (en) * 2018-05-17 2019-08-13 Micron Technology, Inc. Methods of forming a semiconductor structure and methods of forming isolation structures

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5571373A (en) * 1994-05-18 1996-11-05 Memc Electronic Materials, Inc. Method of rough polishing semiconductor wafers to reduce surface roughness
JP3575854B2 (ja) * 1995-02-06 2004-10-13 信越半導体株式会社 シリコン単結晶ウエーハの洗浄方法および洗浄装置
JP3518324B2 (ja) * 1997-03-27 2004-04-12 信越半導体株式会社 シリコンウエーハの熱処理方法およびシリコンウエーハ
JP3451908B2 (ja) * 1997-11-05 2003-09-29 信越半導体株式会社 Ｓｏｉウエーハの熱処理方法およびｓｏｉウエーハ
JPH11354761A (ja) * 1998-06-09 1999-12-24 Sumitomo Metal Ind Ltd Ｓｏｉ基板及びその製造方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2001144275A (ja) * 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウエーハの製造方法および貼り合わせｓｏｉウエーハ
US6376395B2 (en) * 2000-01-11 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
JP2002043318A (ja) * 2000-07-28 2002-02-08 Shin Etsu Handotai Co Ltd シリコン単結晶ウエーハの製造方法
US20020127766A1 (en) * 2000-12-27 2002-09-12 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process

Also Published As

Publication number Publication date
JP2007527604A (ja) 2007-09-27
DE60336687D1 (de) 2011-05-19
AU2003296844A1 (en) 2005-06-24
CN1879205A (zh) 2006-12-13
EP1697981B1 (de) 2011-04-06
EP1697981A1 (de) 2006-09-06
EP1697981B9 (de) 2012-01-25
CN1879205B (zh) 2010-12-01
JP4694372B2 (ja) 2011-06-08
WO2005055307A1 (en) 2005-06-16

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Legal Events

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