ATE492028T1 - Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird - Google Patents
Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wirdInfo
- Publication number
- ATE492028T1 ATE492028T1 AT03763892T AT03763892T ATE492028T1 AT E492028 T1 ATE492028 T1 AT E492028T1 AT 03763892 T AT03763892 T AT 03763892T AT 03763892 T AT03763892 T AT 03763892T AT E492028 T1 ATE492028 T1 AT E492028T1
- Authority
- AT
- Austria
- Prior art keywords
- substrate
- outline
- support
- useful layer
- chamfer
- Prior art date
Links
- 239000000463 material Substances 0.000 title abstract 5
- 239000000758 substrate Substances 0.000 abstract 21
- 239000002131 composite material Substances 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 230000005693 optoelectronics Effects 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/15—Sheet, web, or layer weakened to permit separation through thickness
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/21—Circular sheet or circular blank
- Y10T428/219—Edge structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Silicon Compounds (AREA)
- Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0209017A FR2842646B1 (fr) | 2002-07-17 | 2002-07-17 | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
US46899003P | 2003-05-09 | 2003-05-09 | |
PCT/EP2003/007855 WO2004008527A1 (en) | 2002-07-17 | 2003-07-16 | A method of increasing the area of a useful layer of material transferred onto a support |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE492028T1 true ATE492028T1 (de) | 2011-01-15 |
Family
ID=29797482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03763892T ATE492028T1 (de) | 2002-07-17 | 2003-07-16 | Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird |
Country Status (4)
Country | Link |
---|---|
US (2) | US7048867B2 (de) |
AT (1) | ATE492028T1 (de) |
DE (1) | DE60335388D1 (de) |
FR (1) | FR2842646B1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2842649B1 (fr) * | 2002-07-17 | 2005-06-24 | Soitec Silicon On Insulator | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
JP4525353B2 (ja) * | 2005-01-07 | 2010-08-18 | 住友電気工業株式会社 | Iii族窒化物基板の製造方法 |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US8440541B2 (en) * | 2010-02-25 | 2013-05-14 | Memc Electronic Materials, Inc. | Methods for reducing the width of the unbonded region in SOI structures |
US9156705B2 (en) | 2010-12-23 | 2015-10-13 | Sunedison, Inc. | Production of polycrystalline silicon by the thermal decomposition of dichlorosilane in a fluidized bed reactor |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0636413B2 (ja) * | 1990-03-29 | 1994-05-11 | 信越半導体株式会社 | 半導体素子形成用基板の製造方法 |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP2825048B2 (ja) | 1992-08-10 | 1998-11-18 | 信越半導体株式会社 | 半導体シリコン基板 |
US5597410A (en) * | 1994-09-15 | 1997-01-28 | Yen; Yung C. | Method to make a SOI wafer for IC manufacturing |
US6113721A (en) * | 1995-01-03 | 2000-09-05 | Motorola, Inc. | Method of bonding a semiconductor wafer |
JPH1093122A (ja) | 1996-09-10 | 1998-04-10 | Nippon Telegr & Teleph Corp <Ntt> | 薄膜太陽電池の製造方法 |
FR2774510B1 (fr) * | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
US6664169B1 (en) * | 1999-06-08 | 2003-12-16 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
EP1189266B1 (de) * | 2000-03-29 | 2017-04-05 | Shin-Etsu Handotai Co., Ltd. | Methode zur herstellung einer siliziumhalbleiterscheibe und einer soi-scheibe soiwe soi-scheibe |
JP4846915B2 (ja) | 2000-03-29 | 2011-12-28 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP2001284622A (ja) | 2000-03-31 | 2001-10-12 | Canon Inc | 半導体部材の製造方法及び太陽電池の製造方法 |
JP4628580B2 (ja) * | 2001-04-18 | 2011-02-09 | 信越半導体株式会社 | 貼り合せ基板の製造方法 |
US20040224482A1 (en) * | 2001-12-20 | 2004-11-11 | Kub Francis J. | Method for transferring thin film layer material to a flexible substrate using a hydrogen ion splitting technique |
-
2002
- 2002-07-17 FR FR0209017A patent/FR2842646B1/fr not_active Expired - Lifetime
-
2003
- 2003-07-16 AT AT03763892T patent/ATE492028T1/de not_active IP Right Cessation
- 2003-07-16 US US10/619,446 patent/US7048867B2/en not_active Expired - Lifetime
- 2003-07-16 DE DE60335388T patent/DE60335388D1/de not_active Expired - Lifetime
-
2006
- 2006-02-07 US US11/348,299 patent/US7452584B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20060124584A1 (en) | 2006-06-15 |
FR2842646A1 (fr) | 2004-01-23 |
DE60335388D1 (de) | 2011-01-27 |
FR2842646B1 (fr) | 2005-06-24 |
US7048867B2 (en) | 2006-05-23 |
US7452584B2 (en) | 2008-11-18 |
US20040081790A1 (en) | 2004-04-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |