ATE475987T1 - Zusammenfügen eines substrates mit einem elektrisch leitenden film mit einem zweiten substrat durch molekulare adhäsion - Google Patents

Zusammenfügen eines substrates mit einem elektrisch leitenden film mit einem zweiten substrat durch molekulare adhäsion

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Publication number
ATE475987T1
ATE475987T1 AT05782182T AT05782182T ATE475987T1 AT E475987 T1 ATE475987 T1 AT E475987T1 AT 05782182 T AT05782182 T AT 05782182T AT 05782182 T AT05782182 T AT 05782182T AT E475987 T1 ATE475987 T1 AT E475987T1
Authority
AT
Austria
Prior art keywords
substrate
layer
bond
joining
electrically conductive
Prior art date
Application number
AT05782182T
Other languages
English (en)
Inventor
Hubert Moriceau
Guy Feuillet
Stephane Pocas
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE475987T1 publication Critical patent/ATE475987T1/de

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    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
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    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
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    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Combinations Of Printed Boards (AREA)
  • Laminated Bodies (AREA)
AT05782182T 2004-06-30 2005-06-29 Zusammenfügen eines substrates mit einem elektrisch leitenden film mit einem zweiten substrat durch molekulare adhäsion ATE475987T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0451376A FR2872625B1 (fr) 2004-06-30 2004-06-30 Assemblage par adhesion moleculaire de deux substrats, l'un au moins supportant un film conducteur electrique
PCT/FR2005/050521 WO2006008410A1 (fr) 2004-06-30 2005-06-29 Assemblage par adhesion moleculaire de deux substrats, l'un au moins supportant un film conducteur electrique

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ATE475987T1 true ATE475987T1 (de) 2010-08-15

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US (1) US20080041517A1 (de)
EP (1) EP1774589B1 (de)
AT (1) ATE475987T1 (de)
DE (1) DE602005022588D1 (de)
FR (1) FR2872625B1 (de)
WO (1) WO2006008410A1 (de)

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US7399680B2 (en) * 2004-11-24 2008-07-15 Silicon Genesis Corporation Method and structure for implanting bonded substrates for electrical conductivity
FR2880189B1 (fr) * 2004-12-24 2007-03-30 Tracit Technologies Sa Procede de report d'un circuit sur un plan de masse
FR2956869B1 (fr) 2010-03-01 2014-05-16 Alex Hr Roustaei Systeme de production de film flexible a haute capacite destine a des cellules photovoltaiques et oled par deposition cyclique des couches
US7939369B2 (en) 2009-05-14 2011-05-10 International Business Machines Corporation 3D integration structure and method using bonded metal planes
US9608119B2 (en) 2010-03-02 2017-03-28 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
US8507966B2 (en) * 2010-03-02 2013-08-13 Micron Technology, Inc. Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same
FR2961013B1 (fr) 2010-06-03 2013-05-17 Commissariat Energie Atomique Procede pour eliminer des impuretes residuelles extrinseques dans un substrat en zno ou en znmgo de type n, et pour realiser un dopage de type p de ce substrat.
TWI458072B (zh) * 2010-12-16 2014-10-21 索泰克公司 將半導體構造直接黏附在一起之方法以及應用此等方法所形成之黏附半導體構造
FR2969814A1 (fr) * 2010-12-23 2012-06-29 Soitec Silicon On Insulator Procédés pour lier directement les unes aux autres des structures semi-conductrices, et structures semi-conductrices liées formées en utilisant ces procédés
US8778773B2 (en) 2010-12-16 2014-07-15 Soitec Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
US8952418B2 (en) 2011-03-01 2015-02-10 Micron Technology, Inc. Gated bipolar junction transistors
US8802461B2 (en) 2011-03-22 2014-08-12 Micron Technology, Inc. Vertical light emitting devices with nickel silicide bonding and methods of manufacturing
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
WO2012131075A1 (en) * 2011-03-31 2012-10-04 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
FR2973937B1 (fr) * 2011-04-08 2013-11-01 Soitec Silicon On Insulator Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés
FR2973934B1 (fr) * 2011-04-08 2013-05-03 Soitec Silicon On Insulator Procédés de collage de structures semi-conductrices impliquant des processus de recuit, et structures semi-conductrices collées formées en utilisant ces procédés
TWI471951B (zh) * 2011-03-31 2015-02-01 梭意泰科公司 包含退火程序之半導體結構接合方法，經接合的半導體結構及使用該方法所形成的中間結構
SG194845A1 (en) * 2011-08-30 2013-12-30 Ev Group E Thallner Gmbh Method for permanent bonding of wafers
WO2013154107A1 (ja) * 2012-04-10 2013-10-17 ランテクニカルサービス株式会社 高分子フィルムと高分子フィルムとを接合する方法、高分子フィルムと無機材料基板とを接合する方法、高分子フィルム積層体及び高分子フィルムと無機材料基板との積層体
JP6165127B2 (ja) * 2014-12-22 2017-07-19 三菱重工工作機械株式会社 半導体装置及び半導体装置の製造方法
EP3238241B1 (de) 2014-12-23 2020-03-04 EV Group E. Thallner GmbH Verfahren und vorrichtung zur vorfixierung von substraten
FR3039318B1 (fr) * 2015-07-24 2017-07-21 Commissariat Energie Atomique Procede de controle de cristallisation d’une couche par incorporation d’un element
FR3045939B1 (fr) 2015-12-22 2018-03-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct entre deux structures
FR3098985B1 (fr) * 2019-07-15 2022-04-08 Soitec Silicon On Insulator Procédé de collage hydrophile de substrats

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US6242324B1 (en) * 1999-08-10 2001-06-05 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating singe crystal materials over CMOS devices
FR2798224B1 (fr) * 1999-09-08 2003-08-29 Commissariat Energie Atomique Realisation d'un collage electriquement conducteur entre deux elements semi-conducteurs.

Also Published As

Publication number Publication date
EP1774589A1 (de) 2007-04-18
EP1774589B1 (de) 2010-07-28
FR2872625B1 (fr) 2006-09-22
US20080041517A1 (en) 2008-02-21
FR2872625A1 (fr) 2006-01-06
DE602005022588D1 (de) 2010-09-09
WO2006008410A1 (fr) 2006-01-26

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