FR2973937B1 - Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés - Google Patents

Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés

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Publication number
FR2973937B1
FR2973937B1 FR1153081A FR1153081A FR2973937B1 FR 2973937 B1 FR2973937 B1 FR 2973937B1 FR 1153081 A FR1153081 A FR 1153081A FR 1153081 A FR1153081 A FR 1153081A FR 2973937 B1 FR2973937 B1 FR 2973937B1
Authority
FR
France
Prior art keywords
metal
processes
semiconductor structures
structures
methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1153081A
Other languages
English (en)
Other versions
FR2973937A1 (fr
Inventor
Mariam Sadaka
Ionut Radu
Didier Landru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1153081A priority Critical patent/FR2973937B1/fr
Priority to TW101108739A priority patent/TWI471951B/zh
Priority to PCT/EP2012/055119 priority patent/WO2012130730A1/fr
Publication of FR2973937A1 publication Critical patent/FR2973937A1/fr
Application granted granted Critical
Publication of FR2973937B1 publication Critical patent/FR2973937B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR1153081A 2011-03-31 2011-04-08 Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés Expired - Fee Related FR2973937B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1153081A FR2973937B1 (fr) 2011-04-08 2011-04-08 Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés
TW101108739A TWI471951B (zh) 2011-03-31 2012-03-14 包含退火程序之半導體結構接合方法，經接合的半導體結構及使用該方法所形成的中間結構
PCT/EP2012/055119 WO2012130730A1 (fr) 2011-03-31 2012-03-22 Procédés pour lier des structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées en utilisant ces procédés

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1153081A FR2973937B1 (fr) 2011-04-08 2011-04-08 Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés

Publications (2)

Publication Number Publication Date
FR2973937A1 FR2973937A1 (fr) 2012-10-12
FR2973937B1 true FR2973937B1 (fr) 2013-11-01

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FR1153081A Expired - Fee Related FR2973937B1 (fr) 2011-03-31 2011-04-08 Procédés de collage de structures semi-conductrices comprenant des processus de recuit, et structures semi-conductrices liées et structures intermédiaires formées au moyen de tels procédés

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Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050003652A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
US7193323B2 (en) * 2003-11-18 2007-03-20 International Business Machines Corporation Electroplated CoWP composite structures as copper barrier layers
US20060003548A1 (en) * 2004-06-30 2006-01-05 Kobrinsky Mauro J Highly compliant plate for wafer bonding
FR2872625B1 (fr) * 2004-06-30 2006-09-22 Commissariat Energie Atomique Assemblage par adhesion moleculaire de deux substrats, l'un au moins supportant un film conducteur electrique
US7354862B2 (en) * 2005-04-18 2008-04-08 Intel Corporation Thin passivation layer on 3D devices

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