ATE473483T1 - Verschleierung von speicherzugriffsmustern - Google Patents
Verschleierung von speicherzugriffsmusternInfo
- Publication number
- ATE473483T1 ATE473483T1 AT07254933T AT07254933T ATE473483T1 AT E473483 T1 ATE473483 T1 AT E473483T1 AT 07254933 T AT07254933 T AT 07254933T AT 07254933 T AT07254933 T AT 07254933T AT E473483 T1 ATE473483 T1 AT E473483T1
- Authority
- AT
- Austria
- Prior art keywords
- occasioning
- memory access
- access patterns
- memory
- memory location
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/646,642 US7610448B2 (en) | 2006-12-27 | 2006-12-27 | Obscuring memory access patterns |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE473483T1 true ATE473483T1 (de) | 2010-07-15 |
Family
ID=39314963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT07254933T ATE473483T1 (de) | 2006-12-27 | 2007-12-18 | Verschleierung von speicherzugriffsmustern |
Country Status (5)
Country | Link |
---|---|
US (2) | US7610448B2 (de) |
EP (1) | EP1939752B1 (de) |
CN (1) | CN101231621B (de) |
AT (1) | ATE473483T1 (de) |
DE (1) | DE602007007566D1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7610448B2 (en) * | 2006-12-27 | 2009-10-27 | Intel Corporation | Obscuring memory access patterns |
JP5217432B2 (ja) * | 2007-12-28 | 2013-06-19 | 富士通株式会社 | セクタ機能付きキャッシュメモリ |
CN102436559B (zh) | 2010-09-29 | 2016-06-01 | 联想(北京)有限公司 | 一种状态切换方法及系统 |
US9396135B2 (en) * | 2011-05-18 | 2016-07-19 | University Of North Texas | Method and apparatus for improving computer cache performance and for protecting memory systems against some side channel attacks |
US9495111B2 (en) * | 2014-10-10 | 2016-11-15 | The Boeing Company | System and method for reducing information leakage from memory |
CN105989282B (zh) * | 2015-02-13 | 2019-09-24 | 联想(上海)信息技术有限公司 | 驱动部件控制方法、装置及电子设备 |
US10963567B2 (en) * | 2017-10-12 | 2021-03-30 | Microsoft Technology Licensing, Llc | Speculative side-channel attack mitigations |
US11144468B2 (en) * | 2018-06-29 | 2021-10-12 | Intel Corporation | Hardware based technique to prevent critical fine-grained cache side-channel attacks |
US20190042479A1 (en) * | 2018-06-29 | 2019-02-07 | Intel Corporation | Heuristic and machine-learning based methods to prevent fine-grained cache side-channel attacks |
CN110941569B (zh) * | 2019-11-18 | 2021-01-26 | 新华三半导体技术有限公司 | 数据处理方法、装置及处理器芯片 |
US11704245B2 (en) | 2021-08-31 | 2023-07-18 | Apple Inc. | Dynamic allocation of cache memory as RAM |
US11893251B2 (en) * | 2021-08-31 | 2024-02-06 | Apple Inc. | Allocation of a buffer located in system memory into a cache memory |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5202998A (en) | 1990-08-31 | 1993-04-13 | International Business Machines Corporation | Fast, simultaneous multi-processor system status communication interface |
US5428761A (en) * | 1992-03-12 | 1995-06-27 | Digital Equipment Corporation | System for achieving atomic non-sequential multi-word operations in shared memory |
KR940015822A (ko) | 1992-12-30 | 1994-07-21 | 양승택 | 다중 프로세서 시스템에서 메모리 모듈의 상태변화 시험방법 |
US5555398A (en) | 1994-04-15 | 1996-09-10 | Intel Corporation | Write back cache coherency module for systems with a write through cache supporting bus |
US5794164A (en) * | 1995-11-29 | 1998-08-11 | Microsoft Corporation | Vehicle computer system |
JP3139392B2 (ja) | 1996-10-11 | 2001-02-26 | 日本電気株式会社 | 並列処理システム |
US6026471A (en) * | 1996-11-19 | 2000-02-15 | International Business Machines Corporation | Anticipating cache memory loader and method |
US5974438A (en) * | 1996-12-31 | 1999-10-26 | Compaq Computer Corporation | Scoreboard for cached multi-thread processes |
EP0856798B1 (de) | 1997-01-30 | 2004-09-29 | STMicroelectronics Limited | Cachespeichersystem |
US5909698A (en) | 1997-03-17 | 1999-06-01 | International Business Machines Corporation | Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory |
US6094729A (en) | 1997-04-08 | 2000-07-25 | Advanced Micro Devices, Inc. | Debug interface including a compact trace record storage |
US5974507A (en) | 1997-04-14 | 1999-10-26 | International Business Machines Corporation | Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm |
US6091956A (en) * | 1997-06-12 | 2000-07-18 | Hollenberg; Dennis D. | Situation information system |
US6405049B2 (en) * | 1997-08-05 | 2002-06-11 | Symbol Technologies, Inc. | Portable data terminal and cradle |
US6412056B1 (en) | 1997-10-01 | 2002-06-25 | Compac Information Technologies Group, Lp | Extended translation lookaside buffer with fine-grain state bits |
US6157986A (en) | 1997-12-16 | 2000-12-05 | Advanced Micro Devices, Inc. | Fast linear tag validation unit for use in microprocessor |
US6418542B1 (en) | 1998-04-27 | 2002-07-09 | Sun Microsystems, Inc. | Critical signal thread |
US6189112B1 (en) | 1998-04-30 | 2001-02-13 | International Business Machines Corporation | Transparent processor sparing |
US6282554B1 (en) | 1998-04-30 | 2001-08-28 | Intel Corporation | Method and apparatus for floating point operations and format conversion operations |
US6332181B1 (en) | 1998-05-04 | 2001-12-18 | International Business Machines Corporation | Recovery mechanism for L1 data cache parity errors |
JP3331592B2 (ja) | 1998-05-22 | 2002-10-07 | 日本電気株式会社 | キャッシュメモリ |
JP3585091B2 (ja) * | 1998-06-15 | 2004-11-04 | 富士通株式会社 | 記憶装置 |
US6366946B1 (en) | 1998-12-16 | 2002-04-02 | Microsoft Corporation | Critical code processing management |
US6636950B1 (en) | 1998-12-17 | 2003-10-21 | Massachusetts Institute Of Technology | Computer architecture for shared memory access |
JP2001019464A (ja) * | 1999-07-05 | 2001-01-23 | Sumitomo Electric Ind Ltd | 光ファイバの線引き装置及び線引き方法 |
JP3607540B2 (ja) | 1999-08-18 | 2005-01-05 | エヌイーシーシステムテクノロジー株式会社 | プログラム単位メモリアクセス属性管理方式 |
JP3611295B2 (ja) | 2000-03-09 | 2005-01-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | コンピュータシステム、メモリ管理方法及び記憶媒体 |
US6748496B1 (en) | 2000-04-18 | 2004-06-08 | Ati International Srl | Method and apparatus for providing cacheable data to a peripheral device |
JP2002074922A (ja) * | 2000-08-28 | 2002-03-15 | Pioneer Electronic Corp | 車載用オーディオ及び/又はビデオ装置 |
US6748501B2 (en) | 2000-12-30 | 2004-06-08 | International Business Machines Corporation | Microprocessor reservation mechanism for a hashed address system |
US7184003B2 (en) * | 2001-03-16 | 2007-02-27 | Dualcor Technologies, Inc. | Personal electronics device with display switching |
US7216242B2 (en) * | 2001-03-16 | 2007-05-08 | Dualcor Technologies, Inc. | Personal electronics device with appliance drive features |
JP2002342163A (ja) | 2001-05-15 | 2002-11-29 | Fujitsu Ltd | マルチスレッドプロセッサ用キャッシュ制御方式 |
JP3661614B2 (ja) | 2001-07-12 | 2005-06-15 | 日本電気株式会社 | キャッシュメモリ制御方法及びマルチプロセッサシステム |
DE10134717C2 (de) * | 2001-07-17 | 2003-05-28 | Daimler Chrysler Ag | Verfahren zur Konfiguration eines Informationssystems |
JP4434534B2 (ja) | 2001-09-27 | 2010-03-17 | 株式会社東芝 | プロセッサ・システム |
US6785774B2 (en) | 2001-10-16 | 2004-08-31 | International Business Machines Corporation | High performance symmetric multiprocessing systems via super-coherent data mechanisms |
US6854039B1 (en) | 2001-12-05 | 2005-02-08 | Advanced Micro Devices, Inc. | Memory management system and method providing increased memory access security |
EP1456750A1 (de) | 2001-12-12 | 2004-09-15 | Telefonaktiebolaget LM Ericsson (publ) | Kollisionsbehandlungsvorrichtung und verfahren |
US20030126379A1 (en) | 2001-12-31 | 2003-07-03 | Shiv Kaushik | Instruction sequences for suspending execution of a thread until a specified memory access occurs |
US7215950B2 (en) * | 2002-01-23 | 2007-05-08 | General Motors Corporation | Method of telematics unit configuration and activation using vehicle control buttons |
JP3866597B2 (ja) | 2002-03-20 | 2007-01-10 | 株式会社東芝 | 内部メモリ型耐タンパプロセッサおよび秘密保護方法 |
US7006845B2 (en) * | 2002-04-03 | 2006-02-28 | General Motors Corporation | Method and system for interfacing a portable transceiver in a telematics system |
US6990557B2 (en) * | 2002-06-04 | 2006-01-24 | Sandbridge Technologies, Inc. | Method and apparatus for multithreaded cache with cache eviction based on thread identifier |
US6912623B2 (en) | 2002-06-04 | 2005-06-28 | Sandbridge Technologies, Inc. | Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy |
US7269717B2 (en) | 2003-02-13 | 2007-09-11 | Sun Microsystems, Inc. | Method for reducing lock manipulation overhead during access to critical code sections |
DE10309919B4 (de) | 2003-03-07 | 2008-09-25 | Qimonda Ag | Pufferbaustein und Speichermodule |
US6931504B2 (en) * | 2003-05-06 | 2005-08-16 | Sun Microsystems, Inc. | Method and apparatus for relocating objects within an object-addressed memory hierarchy |
US7089373B2 (en) | 2003-06-12 | 2006-08-08 | International Business Machines Corporation | Shadow register to enhance lock acquisition |
US7047387B2 (en) * | 2003-07-16 | 2006-05-16 | Microsoft Corporation | Block cache size management via virtual memory manager feedback |
US7287126B2 (en) | 2003-07-30 | 2007-10-23 | Intel Corporation | Methods and apparatus for maintaining cache coherency |
US20050138306A1 (en) | 2003-12-19 | 2005-06-23 | Panchbudhe Ankur P. | Performance of operations on selected data in a storage area |
US7114036B2 (en) | 2004-01-14 | 2006-09-26 | International Business Machines Corporation | Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected |
US7562361B2 (en) | 2004-02-26 | 2009-07-14 | Microsoft Corporation | Thread-based limitation on computer application |
US7594234B1 (en) | 2004-06-04 | 2009-09-22 | Sun Microsystems, Inc. | Adaptive spin-then-block mutual exclusion in multi-threaded processing |
US7624236B2 (en) | 2004-12-27 | 2009-11-24 | Intel Corporation | Predictive early write-back of owned cache blocks in a shared memory computer system |
US20070043916A1 (en) | 2005-08-16 | 2007-02-22 | Aguilar Maximino Jr | System and method for light weight task switching when a shared memory condition is signaled |
US8019947B2 (en) | 2005-10-19 | 2011-09-13 | Intel Corporation | Technique for thread communication and synchronization |
US20070124543A1 (en) * | 2005-11-28 | 2007-05-31 | Sudhir Dhawan | Apparatus, system, and method for externally invalidating an uncertain cache line |
US20070124546A1 (en) | 2005-11-29 | 2007-05-31 | Anton Blanchard | Automatic yielding on lock contention for a multi-threaded processor |
US7987452B2 (en) | 2005-12-15 | 2011-07-26 | International Business Machines Corporation | Profile-driven lock handling |
US7991965B2 (en) | 2006-02-07 | 2011-08-02 | Intel Corporation | Technique for using memory attributes |
US7669015B2 (en) * | 2006-02-22 | 2010-02-23 | Sun Microsystems Inc. | Methods and apparatus to implement parallel transactions |
US7831777B2 (en) * | 2006-05-26 | 2010-11-09 | De Mevergnies Michael Neve | Apparatus and method for reducing information leakage between processes sharing a cache |
US7610448B2 (en) | 2006-12-27 | 2009-10-27 | Intel Corporation | Obscuring memory access patterns |
-
2006
- 2006-12-27 US US11/646,642 patent/US7610448B2/en not_active Expired - Fee Related
-
2007
- 2007-12-18 AT AT07254933T patent/ATE473483T1/de not_active IP Right Cessation
- 2007-12-18 EP EP07254933A patent/EP1939752B1/de active Active
- 2007-12-18 DE DE602007007566T patent/DE602007007566D1/de active Active
- 2007-12-27 CN CN2007103035587A patent/CN101231621B/zh not_active Expired - Fee Related
-
2009
- 2009-09-17 US US12/562,041 patent/US8078801B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8078801B2 (en) | 2011-12-13 |
DE602007007566D1 (de) | 2010-08-19 |
EP1939752A1 (de) | 2008-07-02 |
CN101231621B (zh) | 2011-10-19 |
US7610448B2 (en) | 2009-10-27 |
CN101231621A (zh) | 2008-07-30 |
EP1939752B1 (de) | 2010-07-07 |
US20080162816A1 (en) | 2008-07-03 |
US20100299479A1 (en) | 2010-11-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |