BR112015031803A2 - método de gravação de dados e sistema de memória - Google Patents

método de gravação de dados e sistema de memória

Info

Publication number
BR112015031803A2
BR112015031803A2 BR112015031803A BR112015031803A BR112015031803A2 BR 112015031803 A2 BR112015031803 A2 BR 112015031803A2 BR 112015031803 A BR112015031803 A BR 112015031803A BR 112015031803 A BR112015031803 A BR 112015031803A BR 112015031803 A2 BR112015031803 A2 BR 112015031803A2
Authority
BR
Brazil
Prior art keywords
data
memory system
memory
changed
recording method
Prior art date
Application number
BR112015031803A
Other languages
English (en)
Inventor
Jiang Dejun
Xia Fei
Xiong Jin
Original Assignee
Huawei Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Tech Co Ltd filed Critical Huawei Tech Co Ltd
Publication of BR112015031803A2 publication Critical patent/BR112015031803A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

resumo “método de gravação de dados e sistema de memória” as modalidades da presente invenção fornecem um método de gravação de dados e um sistema de memória. o método é aplicado a um sistema de memória que inclui pelo menos um controlador de memória e um dispositivo de memória, e o método inclui: receber, pelo controlador de memória, informações de alteração enviadas por um armazenamento intermediário de provisão, em que as informações de alteração são informações que são geradas após o armazenamento intermediário de provisão dividir uma primeira linha de armazenamento intermediário de provisão a ser gravada de um armazenamento intermediário de provisão de último nível llc em pelo menos um bloco de dados e que são usadas para indicar se os dados em cada bloco de dados são alterados; enviar, para cada bloco de dados alterado no qual os dados são alterados, pelo controlador de memória em conformidade com as informações de alteração, um endereço de coluna correspondente e dados correspondentes ao dispositivos de memória; e ignorar a realização, para um bloco de dados no qual os dados não são alterados, pelo controlador de memória em conformidade com as informações de alteração, uma gravação. portanto, os objetivos para gravar rapidamente dados válidos, reduzir o consumo de energia de um sistema de memória e melhorar o desempenho do sistema de memória são alcançados. 1/1
BR112015031803A 2013-06-29 2014-06-17 método de gravação de dados e sistema de memória BR112015031803A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310270239.6A CN104252420B (zh) 2013-06-29 2013-06-29 数据写入方法及内存系统
PCT/CN2014/080073 WO2014206220A1 (zh) 2013-06-29 2014-06-17 数据写入方法及内存系统

Publications (1)

Publication Number Publication Date
BR112015031803A2 true BR112015031803A2 (pt) 2017-07-25

Family

ID=52141031

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015031803A BR112015031803A2 (pt) 2013-06-29 2014-06-17 método de gravação de dados e sistema de memória

Country Status (9)

Country Link
US (1) US20160110286A1 (pt)
EP (1) EP2998867B1 (pt)
JP (1) JP6159478B2 (pt)
KR (1) KR101785189B1 (pt)
CN (2) CN104252420B (pt)
AU (1) AU2014301874B2 (pt)
BR (1) BR112015031803A2 (pt)
RU (1) RU2621611C1 (pt)
WO (1) WO2014206220A1 (pt)

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CN111857822B (zh) * 2016-08-05 2024-04-05 中科寒武纪科技股份有限公司 一种运算装置及其操作方法
CN109324982B (zh) * 2017-07-31 2023-06-27 上海华为技术有限公司 一种数据处理方法以及数据处理装置
US20210200695A1 (en) * 2019-12-27 2021-07-01 Advanced Micro Devices, Inc. Staging memory access requests
CN113821256A (zh) * 2021-08-19 2021-12-21 浙江大华技术股份有限公司 数据读写方法、装置、计算机设备和存储介质
CN113918508A (zh) * 2021-12-15 2022-01-11 苏州浪潮智能科技有限公司 一种缓存加速方法、装置、设备及可读存储介质
CN117396857A (zh) * 2021-12-21 2024-01-12 华为技术有限公司 一种数据存储方法、存储装置及设备

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Also Published As

Publication number Publication date
CN107577614B (zh) 2020-10-16
CN104252420B (zh) 2017-08-29
EP2998867A1 (en) 2016-03-23
EP2998867B1 (en) 2019-09-18
JP2016524251A (ja) 2016-08-12
US20160110286A1 (en) 2016-04-21
JP6159478B2 (ja) 2017-07-05
RU2621611C1 (ru) 2017-06-06
KR101785189B1 (ko) 2017-10-12
AU2014301874A1 (en) 2016-01-21
EP2998867A4 (en) 2016-07-06
WO2014206220A1 (zh) 2014-12-31
CN107577614A (zh) 2018-01-12
KR20160014053A (ko) 2016-02-05
CN104252420A (zh) 2014-12-31
AU2014301874B2 (en) 2017-05-04

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B27A Filing of a green patent (patente verde) [chapter 27.1 patent gazette]
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2518 DE 09-04-2019 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.

B350 Update of information on the portal [chapter 15.35 patent gazette]