BR112015029854A2 - mapeamento de endereço de ecc incorporado - Google Patents

mapeamento de endereço de ecc incorporado

Info

Publication number
BR112015029854A2
BR112015029854A2 BR112015029854A BR112015029854A BR112015029854A2 BR 112015029854 A2 BR112015029854 A2 BR 112015029854A2 BR 112015029854 A BR112015029854 A BR 112015029854A BR 112015029854 A BR112015029854 A BR 112015029854A BR 112015029854 A2 BR112015029854 A2 BR 112015029854A2
Authority
BR
Brazil
Prior art keywords
data
memory
address mapping
memory page
error correction
Prior art date
Application number
BR112015029854A
Other languages
English (en)
Inventor
D Vogt Pete
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015029854A2 publication Critical patent/BR112015029854A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1052—Bypassing or disabling error detection or correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

resumo patente de invenção: "mapeamento de endereço de ecc incorporado". são descritos aparelhos, sistemas e métodos para incorporar os dados de ecc aos dados de linha de cache em uma página de memória. em uma modalidade, um dispositivo eletrônico compreende um processador e uma lógica de controle de memória para receber uma solicitação para ler ou gravar dados em um dispositivo de memória, em que os dados são mapeados para uma página de memória que compreende uma pluralidade de linhas de cache, deslocar pelo menos uma porção da pluralidade de linhas de cache para incorporar as informações de código de correção de erro aos dados, e remapear a porção da pluralidade de linhas de cache para outro local de memória, e recuperar ou armazenar os dados e as informações de código de correção de erro na página de memória. outras modalidades são reveladas e reivindicadas.
BR112015029854A 2013-06-28 2014-06-24 mapeamento de endereço de ecc incorporado BR112015029854A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/930,600 US10031802B2 (en) 2013-06-28 2013-06-28 Embedded ECC address mapping
PCT/US2014/043766 WO2014209936A1 (en) 2013-06-28 2014-06-24 Embedded ecc address mapping

Publications (1)

Publication Number Publication Date
BR112015029854A2 true BR112015029854A2 (pt) 2017-07-25

Family

ID=52116923

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015029854A BR112015029854A2 (pt) 2013-06-28 2014-06-24 mapeamento de endereço de ecc incorporado

Country Status (8)

Country Link
US (1) US10031802B2 (pt)
EP (1) EP3014227A4 (pt)
JP (1) JP6231194B2 (pt)
KR (1) KR101732841B1 (pt)
CN (1) CN105264342B (pt)
BR (1) BR112015029854A2 (pt)
RU (1) RU2644529C2 (pt)
WO (1) WO2014209936A1 (pt)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10031802B2 (en) 2013-06-28 2018-07-24 Intel Corporation Embedded ECC address mapping
US9954557B2 (en) * 2014-04-30 2018-04-24 Microsoft Technology Licensing, Llc Variable width error correction
US10268541B2 (en) * 2016-08-15 2019-04-23 Samsung Electronics Co., Ltd. DRAM assist error correction mechanism for DDR SDRAM interface
US10853168B2 (en) * 2018-03-28 2020-12-01 Samsung Electronics Co., Ltd. Apparatus to insert error-correcting coding (ECC) information as data within dynamic random access memory (DRAM)
US11307771B2 (en) * 2020-07-10 2022-04-19 Micron Technology, Inc. Configurable link interfaces for a memory device
US11288188B1 (en) * 2021-01-21 2022-03-29 Qualcomm Incorporated Dynamic metadata relocation in memory

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6467048B1 (en) * 1999-10-07 2002-10-15 Compaq Information Technologies Group, L.P. Apparatus, method and system for using cache memory as fail-over memory
US6427188B1 (en) * 2000-02-09 2002-07-30 Hewlett-Packard Company Method and system for early tag accesses for lower-level caches in parallel with first-level cache
US6996766B2 (en) 2002-06-28 2006-02-07 Sun Microsystems, Inc. Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
US6961821B2 (en) 2002-10-16 2005-11-01 International Business Machines Corporation Reconfigurable cache controller for nonuniform memory access computer systems
US7234099B2 (en) 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US7149945B2 (en) 2003-05-09 2006-12-12 Hewlett-Packard Development Company, L.P. Systems and methods for providing error correction code testing functionality
JP3714558B2 (ja) 2003-10-10 2005-11-09 ソニー株式会社 ファイル管理装置、ファイル管理方法、ファイル管理方法のプログラム及びファイル管理方法のプログラムを記録した記録媒体
US7124254B2 (en) * 2004-05-05 2006-10-17 Sun Microsystems, Inc. Method and structure for monitoring pollution and prefetches due to speculative accesses
US20060218467A1 (en) 2005-03-24 2006-09-28 Sibigtroth James M Memory having a portion that can be switched between use as data and use as error correction code (ECC)
US7650558B2 (en) * 2005-08-16 2010-01-19 Intel Corporation Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems
US7774684B2 (en) 2006-06-30 2010-08-10 Intel Corporation Reliability, availability, and serviceability in a memory device
US7890836B2 (en) 2006-12-14 2011-02-15 Intel Corporation Method and apparatus of cache assisted error detection and correction in memory
US8464138B2 (en) 2008-08-20 2013-06-11 Qualcomm Incorporated Effective utilization of header space for error correction in aggregate frames
US8291259B2 (en) 2009-04-15 2012-10-16 International Business Machines Corporation Delete of cache line with correctable error
JP5414350B2 (ja) 2009-05-08 2014-02-12 キヤノン株式会社 メモリ制御回路、及び、その制御方法
US8495464B2 (en) * 2010-06-28 2013-07-23 Intel Corporation Reliability support in memory systems without error correcting code support
US8719664B1 (en) * 2011-04-12 2014-05-06 Sk Hynix Memory Solutions Inc. Memory protection cache
US9003247B2 (en) * 2011-04-28 2015-04-07 Hewlett-Packard Development Company, L.P. Remapping data with pointer
US9391637B2 (en) * 2012-03-30 2016-07-12 Intel Corporation Error correcting code scheme utilizing reserved space
CN103019963B (zh) 2012-12-31 2016-07-06 华为技术有限公司 一种高速缓存的映射方法及存储设备
US10031802B2 (en) 2013-06-28 2018-07-24 Intel Corporation Embedded ECC address mapping

Also Published As

Publication number Publication date
RU2015151167A (ru) 2017-06-01
EP3014227A1 (en) 2016-05-04
WO2014209936A1 (en) 2014-12-31
RU2644529C2 (ru) 2018-02-12
EP3014227A4 (en) 2017-02-22
KR101732841B1 (ko) 2017-05-04
JP2016520937A (ja) 2016-07-14
US10031802B2 (en) 2018-07-24
US20150006993A1 (en) 2015-01-01
CN105264342A (zh) 2016-01-20
CN105264342B (zh) 2019-05-14
KR20150143598A (ko) 2015-12-23
JP6231194B2 (ja) 2017-11-15

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B06A Notification to applicant to reply to the report for non-patentability or inadequacy of the application [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B11D Dismissal acc. art. 38, par 2 of ipl - failure to pay fee after grant in time
B350 Update of information on the portal [chapter 15.35 patent gazette]