ATE472768T1 - Verbesserungen im bezug auf orthogonal- datenspeicher - Google Patents
Verbesserungen im bezug auf orthogonal- datenspeicherInfo
- Publication number
- ATE472768T1 ATE472768T1 AT05717960T AT05717960T ATE472768T1 AT E472768 T1 ATE472768 T1 AT E472768T1 AT 05717960 T AT05717960 T AT 05717960T AT 05717960 T AT05717960 T AT 05717960T AT E472768 T1 ATE472768 T1 AT E472768T1
- Authority
- AT
- Austria
- Prior art keywords
- data
- memory cells
- groups
- word
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
- G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Circuits Of Receivers In General (AREA)
- Dram (AREA)
- Multi Processors (AREA)
- Image Processing (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0405283.3A GB0405283D0 (en) | 2004-03-09 | 2004-03-09 | Multi-port memory for flexible and space efficient corner turning networks in associative processors |
PCT/GB2005/000895 WO2005088640A2 (en) | 2004-03-09 | 2005-03-09 | Improvements relating to orthogonal data memory |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE472768T1 true ATE472768T1 (de) | 2010-07-15 |
Family
ID=32117330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT05717960T ATE472768T1 (de) | 2004-03-09 | 2005-03-09 | Verbesserungen im bezug auf orthogonal- datenspeicher |
Country Status (6)
Country | Link |
---|---|
US (1) | US20080162824A1 (de) |
EP (1) | EP1733300B1 (de) |
AT (1) | ATE472768T1 (de) |
DE (1) | DE602005022058D1 (de) |
GB (1) | GB0405283D0 (de) |
WO (1) | WO2005088640A2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7369422B2 (en) * | 2006-02-23 | 2008-05-06 | Laurence Hager Cooke | Serial content addressable memory |
US8085567B2 (en) * | 2006-02-23 | 2011-12-27 | Cooke Laurence H | Iterative serial content addressable memory |
US8656143B2 (en) * | 2006-03-13 | 2014-02-18 | Laurence H. Cooke | Variable clocked heterogeneous serial array processor |
US20070226455A1 (en) * | 2006-03-13 | 2007-09-27 | Cooke Laurence H | Variable clocked heterogeneous serial array processor |
EP2138937A4 (de) * | 2007-04-12 | 2011-01-26 | Nec Corp | Datenverarbeitungsvorrichtung des arrayprozessortyps |
US20110051485A1 (en) * | 2009-08-28 | 2011-03-03 | International Business Machines Corporation | Content addressable memory array writing |
US8189408B2 (en) * | 2009-11-17 | 2012-05-29 | Freescale Semiconductor, Inc. | Memory device having shifting capability and method thereof |
US9899070B2 (en) * | 2016-02-19 | 2018-02-20 | Micron Technology, Inc. | Modified decode for corner turn |
CN110337635B (zh) | 2017-03-20 | 2023-09-19 | 英特尔公司 | 用于点积操作的系统、方法和装置 |
WO2019009870A1 (en) | 2017-07-01 | 2019-01-10 | Intel Corporation | SAVE BACKGROUND TO VARIABLE BACKUP STATUS SIZE |
US11740899B2 (en) * | 2021-08-31 | 2023-08-29 | Micron Technology, Inc. | In-memory associative processing system |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3681763A (en) * | 1970-05-01 | 1972-08-01 | Cogar Corp | Semiconductor orthogonal memory systems |
US3936806A (en) * | 1972-07-12 | 1976-02-03 | Goodyear Aerospace Corporation | Solid state associative processor organization |
GB8414109D0 (en) * | 1984-06-02 | 1984-07-04 | Int Computers Ltd | Data reorganisation apparatus |
GB2160685B (en) * | 1984-06-02 | 1987-09-03 | Int Computers Ltd | Data reorganisation apparatus |
JP2588195B2 (ja) * | 1987-05-28 | 1997-03-05 | 株式会社東芝 | パルス入力装置 |
EP0424618A3 (en) * | 1989-10-24 | 1992-11-19 | International Business Machines Corporation | Input/output system |
US5101371A (en) * | 1990-06-04 | 1992-03-31 | The United States Of America As Represented By The Director Of The National Security Agency | Apparatus for performing a bit serial orthogonal transformation instruction |
US5612964A (en) * | 1991-04-08 | 1997-03-18 | Haraszti; Tegze P. | High performance, fault tolerant orthogonal shuffle memory and method |
US5581773A (en) * | 1992-05-12 | 1996-12-03 | Glover; Michael A. | Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements |
US5450604A (en) * | 1992-12-18 | 1995-09-12 | Xerox Corporation | Data rotation using parallel to serial units that receive data from memory units and rotation buffer that provides rotated data to memory units |
JP2997613B2 (ja) * | 1993-10-26 | 2000-01-11 | 株式会社東芝 | 離散コサイン変換装置 |
JP3133601B2 (ja) * | 1994-02-09 | 2001-02-13 | 株式会社東芝 | パラレル・シリアル変換装置及びこれを用いた線形変換装置 |
US6292433B1 (en) * | 1997-02-03 | 2001-09-18 | Teratech Corporation | Multi-dimensional beamforming device |
US6173388B1 (en) * | 1998-04-09 | 2001-01-09 | Teranex Inc. | Directly accessing local memories of array processors for improved real-time corner turning processing |
US6684275B1 (en) * | 1998-10-23 | 2004-01-27 | Octave Communications, Inc. | Serial-to-parallel/parallel-to-serial conversion engine |
US20020032710A1 (en) * | 2000-03-08 | 2002-03-14 | Ashley Saulsbury | Processing architecture having a matrix-transpose capability |
US20020093508A1 (en) * | 2001-01-18 | 2002-07-18 | Lightsurf Technologies, Inc. | Orthogonal memory for digital imaging devices |
US6781898B2 (en) * | 2002-10-30 | 2004-08-24 | Broadcom Corporation | Self-repairing built-in self test for linked list memories |
US20040111567A1 (en) * | 2002-12-05 | 2004-06-10 | Anderson Adrian John | SIMD processor with multi-port memory unit |
-
2004
- 2004-03-09 GB GBGB0405283.3A patent/GB0405283D0/en not_active Ceased
-
2005
- 2005-03-09 US US10/591,922 patent/US20080162824A1/en not_active Abandoned
- 2005-03-09 EP EP05717960A patent/EP1733300B1/de not_active Not-in-force
- 2005-03-09 AT AT05717960T patent/ATE472768T1/de not_active IP Right Cessation
- 2005-03-09 DE DE602005022058T patent/DE602005022058D1/de active Active
- 2005-03-09 WO PCT/GB2005/000895 patent/WO2005088640A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US20080162824A1 (en) | 2008-07-03 |
WO2005088640A3 (en) | 2005-10-27 |
WO2005088640A9 (en) | 2005-12-15 |
WO2005088640A2 (en) | 2005-09-22 |
EP1733300A2 (de) | 2006-12-20 |
EP1733300B1 (de) | 2010-06-30 |
GB0405283D0 (en) | 2004-04-21 |
DE602005022058D1 (de) | 2010-08-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |