ATE367608T1 - Integrierte schaltung mit bimodalem daten-strobe - Google Patents
Integrierte schaltung mit bimodalem daten-strobeInfo
- Publication number
- ATE367608T1 ATE367608T1 AT04783434T AT04783434T ATE367608T1 AT E367608 T1 ATE367608 T1 AT E367608T1 AT 04783434 T AT04783434 T AT 04783434T AT 04783434 T AT04783434 T AT 04783434T AT E367608 T1 ATE367608 T1 AT E367608T1
- Authority
- AT
- Austria
- Prior art keywords
- data strobe
- data
- integrated circuit
- mode
- memory device
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/676,648 US20050071707A1 (en) | 2003-09-30 | 2003-09-30 | Integrated circuit with bi-modal data strobe |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE367608T1 true ATE367608T1 (de) | 2007-08-15 |
Family
ID=34377433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04783434T ATE367608T1 (de) | 2003-09-30 | 2004-09-03 | Integrierte schaltung mit bimodalem daten-strobe |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US20050071707A1 (enExample) |
| EP (1) | EP1668523B2 (enExample) |
| JP (2) | JP4783290B2 (enExample) |
| KR (2) | KR101110469B1 (enExample) |
| AT (1) | ATE367608T1 (enExample) |
| DE (1) | DE602004007674T3 (enExample) |
| WO (1) | WO2005033958A1 (enExample) |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8422568B2 (en) | 2004-01-28 | 2013-04-16 | Rambus Inc. | Communication channel calibration for drift conditions |
| US7400670B2 (en) | 2004-01-28 | 2008-07-15 | Rambus, Inc. | Periodic calibration for communication channels by drift tracking |
| US7095789B2 (en) | 2004-01-28 | 2006-08-22 | Rambus, Inc. | Communication channel calibration for drift conditions |
| US6961862B2 (en) * | 2004-03-17 | 2005-11-01 | Rambus, Inc. | Drift tracking feedback for communication channels |
| US7296129B2 (en) | 2004-07-30 | 2007-11-13 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
| US7171321B2 (en) * | 2004-08-20 | 2007-01-30 | Rambus Inc. | Individual data line strobe-offset control in memory systems |
| US7299313B2 (en) | 2004-10-29 | 2007-11-20 | International Business Machines Corporation | System, method and storage medium for a memory subsystem command interface |
| US7512762B2 (en) * | 2004-10-29 | 2009-03-31 | International Business Machines Corporation | System, method and storage medium for a memory subsystem with positional read data latency |
| US7331010B2 (en) | 2004-10-29 | 2008-02-12 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
| US7441060B2 (en) | 2004-10-29 | 2008-10-21 | International Business Machines Corporation | System, method and storage medium for providing a service interface to a memory system |
| US20060095620A1 (en) * | 2004-10-29 | 2006-05-04 | International Business Machines Corporation | System, method and storage medium for merging bus data in a memory subsystem |
| US7543172B2 (en) | 2004-12-21 | 2009-06-02 | Rambus Inc. | Strobe masking in a signaling system having multiple clock domains |
| US7688672B2 (en) * | 2005-03-14 | 2010-03-30 | Rambus Inc. | Self-timed interface for strobe-based systems |
| US7478259B2 (en) * | 2005-10-31 | 2009-01-13 | International Business Machines Corporation | System, method and storage medium for deriving clocks in a memory system |
| US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
| US8121237B2 (en) * | 2006-03-16 | 2012-02-21 | Rambus Inc. | Signaling system with adaptive timing calibration |
| US7636813B2 (en) | 2006-05-22 | 2009-12-22 | International Business Machines Corporation | Systems and methods for providing remote pre-fetch buffers |
| US7640386B2 (en) | 2006-05-24 | 2009-12-29 | International Business Machines Corporation | Systems and methods for providing memory modules with multiple hub devices |
| US7594055B2 (en) * | 2006-05-24 | 2009-09-22 | International Business Machines Corporation | Systems and methods for providing distributed technology independent memory controllers |
| US7702832B2 (en) * | 2006-06-07 | 2010-04-20 | Standard Microsystems Corporation | Low power and low pin count bi-directional dual data rate device interconnect interface |
| JP4267002B2 (ja) | 2006-06-08 | 2009-05-27 | エルピーダメモリ株式会社 | コントローラ及びメモリを備えるシステム |
| US7584336B2 (en) | 2006-06-08 | 2009-09-01 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
| US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
| US7581073B2 (en) | 2006-08-09 | 2009-08-25 | International Business Machines Corporation | Systems and methods for providing distributed autonomous power management in a memory system |
| US7587559B2 (en) | 2006-08-10 | 2009-09-08 | International Business Machines Corporation | Systems and methods for memory module power management |
| US7539842B2 (en) | 2006-08-15 | 2009-05-26 | International Business Machines Corporation | Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables |
| US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
| US7721140B2 (en) * | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
| US7606988B2 (en) | 2007-01-29 | 2009-10-20 | International Business Machines Corporation | Systems and methods for providing a dynamic memory bank page policy |
| US7603526B2 (en) | 2007-01-29 | 2009-10-13 | International Business Machines Corporation | Systems and methods for providing dynamic memory pre-fetch |
| US8868873B2 (en) | 2007-09-27 | 2014-10-21 | Rambus Inc. | Reconfigurable memory system data strobes |
| EP3719803B1 (en) | 2007-12-21 | 2025-05-07 | Rambus Inc. | Method and apparatus for calibrating write timing in a memory system |
| US8521979B2 (en) * | 2008-05-29 | 2013-08-27 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
| US7979757B2 (en) | 2008-06-03 | 2011-07-12 | Micron Technology, Inc. | Method and apparatus for testing high capacity/high bandwidth memory devices |
| US8289760B2 (en) | 2008-07-02 | 2012-10-16 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
| US7855931B2 (en) | 2008-07-21 | 2010-12-21 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
| US8756486B2 (en) * | 2008-07-02 | 2014-06-17 | Micron Technology, Inc. | Method and apparatus for repairing high capacity/high bandwidth memory devices |
| US8127204B2 (en) | 2008-08-15 | 2012-02-28 | Micron Technology, Inc. | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system |
| EP2384474B1 (en) * | 2008-12-31 | 2015-08-12 | Rambus Inc. | Active calibration for high-speed memory devices |
| US8627160B2 (en) * | 2010-04-21 | 2014-01-07 | Lsi Corporation | System and device for reducing instantaneous voltage droop during a scan shift operation |
| US8400808B2 (en) | 2010-12-16 | 2013-03-19 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
| EP2774151B1 (en) * | 2011-11-01 | 2019-08-14 | Rambus Inc. | Data transmission using delayed timing signals |
| US9032356B2 (en) | 2013-03-06 | 2015-05-12 | Lsi Corporation | Programmable clock spreading |
| RU2623801C1 (ru) | 2013-07-26 | 2017-06-29 | Интел Корпорейшн | Интерфейс энергонезависимой памяти |
| US9171597B2 (en) | 2013-08-30 | 2015-10-27 | Micron Technology, Inc. | Apparatuses and methods for providing strobe signals to memories |
| US9660847B2 (en) | 2014-11-26 | 2017-05-23 | Rambus Inc. | Equalized multi-signaling mode driver |
| US10325636B1 (en) | 2017-05-01 | 2019-06-18 | Rambus Inc. | Signal receiver with skew-tolerant strobe gating |
| CN119851706A (zh) | 2019-02-27 | 2025-04-18 | 拉姆伯斯公司 | 具有按需带宽提升的低功率存储器 |
| US11127444B1 (en) | 2019-08-20 | 2021-09-21 | Rambus Inc. | Signal receiver with skew-tolerant strobe gating |
| WO2023038790A1 (en) * | 2021-09-07 | 2023-03-16 | Rambus Inc. | Common data strobe among multiple memory devices |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721860A (en) * | 1994-05-24 | 1998-02-24 | Intel Corporation | Memory controller for independently supporting synchronous and asynchronous DRAM memories |
| US5692165A (en) * | 1995-09-12 | 1997-11-25 | Micron Electronics Inc. | Memory controller with low skew control signal |
| JP3929116B2 (ja) * | 1997-07-04 | 2007-06-13 | 富士通株式会社 | メモリサブシステム |
| JP3922765B2 (ja) * | 1997-07-22 | 2007-05-30 | 富士通株式会社 | 半導体装置システム及び半導体装置 |
| US6085285A (en) * | 1997-11-13 | 2000-07-04 | International Business Machines Corporation | Intermixing different devices along a single data communication link by placing a strobe signal in a parity bit slot |
| US6487647B1 (en) * | 1997-12-29 | 2002-11-26 | Intel Corporation | Adaptive memory interface timing generation |
| US6510503B2 (en) * | 1998-07-27 | 2003-01-21 | Mosaid Technologies Incorporated | High bandwidth memory interface |
| DE19839105B4 (de) * | 1998-08-27 | 2006-04-06 | Infineon Technologies Ag | Integrierter Halbleiterspeicher mit Steuerungseinrichtung zum taktsynchronen Schreiben und Lesen |
| JP2000163965A (ja) * | 1998-11-27 | 2000-06-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| US6621496B1 (en) * | 1999-02-26 | 2003-09-16 | Micron Technology, Inc. | Dual mode DDR SDRAM/SGRAM |
| US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
| JP2002007200A (ja) * | 2000-06-16 | 2002-01-11 | Nec Corp | メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体 |
| US7134960B1 (en) * | 2000-08-23 | 2006-11-14 | Nintendo Co., Ltd. | External interfaces for a 3D graphics system |
| US6502173B1 (en) * | 2000-09-29 | 2002-12-31 | Ati Technologies, Inc. | System for accessing memory and method therefore |
| US20020144173A1 (en) * | 2001-03-30 | 2002-10-03 | Micron Technology, Inc. | Serial presence detect driven memory clock control |
| JP2003007069A (ja) * | 2001-06-18 | 2003-01-10 | Mitsubishi Electric Corp | 半導体記憶装置および半導体集積回路装置 |
| JP4768163B2 (ja) * | 2001-08-03 | 2011-09-07 | 富士通セミコンダクター株式会社 | 半導体メモリ |
| JP2003050739A (ja) * | 2001-08-06 | 2003-02-21 | Matsushita Electric Ind Co Ltd | メモリ制御装置 |
| US7062625B1 (en) * | 2001-09-14 | 2006-06-13 | Denali Software, Inc. | Input/output cells for a double data rate (DDR) memory controller |
| TW563132B (en) * | 2001-10-09 | 2003-11-21 | Via Tech Inc | Common DRAM controller supports double-data-rate and quad-data-rate memory |
| US6944738B2 (en) * | 2002-04-16 | 2005-09-13 | Sun Microsystems, Inc. | Scalable design for DDR SDRAM buses |
| US20040003194A1 (en) * | 2002-06-26 | 2004-01-01 | Amit Bodas | Method and apparatus for adjusting DRAM signal timings |
| US7093082B2 (en) * | 2003-06-11 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd | Microprogrammable SDRAM memory interface controller |
| KR100626375B1 (ko) * | 2003-07-21 | 2006-09-20 | 삼성전자주식회사 | 고주파로 동작하는 반도체 메모리 장치 및 모듈 |
| US6853594B1 (en) * | 2003-07-22 | 2005-02-08 | Sun Microsystems, Inc. | Double data rate (DDR) data strobe receiver |
| US8289032B2 (en) | 2007-03-20 | 2012-10-16 | Rambus Inc. | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement |
-
2003
- 2003-09-30 US US10/676,648 patent/US20050071707A1/en not_active Abandoned
-
2004
- 2004-09-03 AT AT04783434T patent/ATE367608T1/de not_active IP Right Cessation
- 2004-09-03 EP EP04783434.6A patent/EP1668523B2/en not_active Expired - Lifetime
- 2004-09-03 KR KR1020067008404A patent/KR101110469B1/ko not_active Expired - Fee Related
- 2004-09-03 JP JP2006533897A patent/JP4783290B2/ja not_active Expired - Fee Related
- 2004-09-03 DE DE602004007674.0T patent/DE602004007674T3/de not_active Expired - Lifetime
- 2004-09-03 WO PCT/US2004/029186 patent/WO2005033958A1/en not_active Ceased
- 2004-09-03 KR KR1020117006938A patent/KR101108297B1/ko not_active Expired - Fee Related
-
2008
- 2008-04-15 US US12/103,640 patent/US8352696B2/en not_active Expired - Fee Related
-
2011
- 2011-03-08 JP JP2011050556A patent/JP5191555B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR101108297B1 (ko) | 2012-01-25 |
| WO2005033958A1 (en) | 2005-04-14 |
| US20050071707A1 (en) | 2005-03-31 |
| DE602004007674D1 (de) | 2007-08-30 |
| JP4783290B2 (ja) | 2011-09-28 |
| EP1668523B2 (en) | 2014-12-10 |
| EP1668523B1 (en) | 2007-07-18 |
| US20080195885A1 (en) | 2008-08-14 |
| JP2007507794A (ja) | 2007-03-29 |
| KR101110469B1 (ko) | 2012-01-31 |
| DE602004007674T2 (de) | 2008-04-10 |
| KR20110038184A (ko) | 2011-04-13 |
| EP1668523A1 (en) | 2006-06-14 |
| KR20060111465A (ko) | 2006-10-27 |
| US8352696B2 (en) | 2013-01-08 |
| DE602004007674T3 (de) | 2015-05-28 |
| JP2011146063A (ja) | 2011-07-28 |
| JP5191555B2 (ja) | 2013-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE367608T1 (de) | Integrierte schaltung mit bimodalem daten-strobe | |
| ATE444555T1 (de) | Festphasentakt und strobe-signale in verketteten chips | |
| WO2002039460A3 (en) | Full-speed bist controller for testing embedded synchronous memories | |
| TW200721166A (en) | Semiconductor memories with block-dedicated programmable latency register | |
| TWI257099B (en) | Integrated circuit device for providing selectively variable write latency and method thereof | |
| DE60315165D1 (de) | Verfahren und vorrichtung zum einstellen und kompensieren der leselatenz in einem hochgeschwindigkeits-dram | |
| ATE532182T1 (de) | Erfassung von lesedaten in einem synchrondatenspeicher | |
| WO2005041055A3 (en) | Echo clock on memory system having wait information | |
| TW200615944A (en) | Memory hub tester interface and method for use thereof | |
| TW368653B (en) | Synchronized semiconductor memory device for reducing the power consumption during standby | |
| EP1298667A3 (en) | Semiconductor memory device | |
| RU2013107936A (ru) | Устройство usb-ключа и способ подключения смарт-карты с помощью интерфейса usb | |
| WO2002017323A3 (en) | Synchronized write data on a high speed memory bus | |
| TW200615975A (en) | Data output circuit of memory device | |
| TW200506965A (en) | Data input unit of synchronous semiconductor memory device, and data input method using the same | |
| TW200511314A (en) | Synchronous memory device having advanced data align circuit | |
| EP1168369A3 (en) | Synchronous semiconductor memory device | |
| ATE507563T1 (de) | Rekonstruktion des signal-timing in integrierten schaltungen | |
| ATE363715T1 (de) | Speicherbaustein mit mehrfunktions-strobe- anschlüssen | |
| WO2006081057A3 (en) | Simultaneous pipelined read with dual level cache for improved system performance using flash technology | |
| WO2003090231A3 (en) | Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device | |
| TW200639808A (en) | Signal processing circuits and methods, and memory systems | |
| US7876641B2 (en) | Semiconductor integrated circuit | |
| CN1933015A (zh) | 半导体集成电路器件 | |
| TW200631025A (en) | Method and system for timing measurement of embedded macro module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |