ATE36425T1 - Bildwiederholspeicher-architektur mit schnellem zugriff fuer eine graphische anzeigeeinrichtung. - Google Patents

Bildwiederholspeicher-architektur mit schnellem zugriff fuer eine graphische anzeigeeinrichtung.

Info

Publication number
ATE36425T1
ATE36425T1 AT83300657T AT83300657T ATE36425T1 AT E36425 T1 ATE36425 T1 AT E36425T1 AT 83300657 T AT83300657 T AT 83300657T AT 83300657 T AT83300657 T AT 83300657T AT E36425 T1 ATE36425 T1 AT E36425T1
Authority
AT
Austria
Prior art keywords
display
address
storage locations
access
memory
Prior art date
Application number
AT83300657T
Other languages
English (en)
Inventor
Robert Alan Bruce
Original Assignee
Metheus Corp Formerly Metheus
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Metheus Corp Formerly Metheus filed Critical Metheus Corp Formerly Metheus
Application granted granted Critical
Publication of ATE36425T1 publication Critical patent/ATE36425T1/de

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Image Generation (AREA)
  • Digital Computer Display Output (AREA)
AT83300657T 1982-02-12 1983-02-10 Bildwiederholspeicher-architektur mit schnellem zugriff fuer eine graphische anzeigeeinrichtung. ATE36425T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/348,517 US4546451A (en) 1982-02-12 1982-02-12 Raster graphics display refresh memory architecture offering rapid access speed
EP83300657A EP0087868B1 (de) 1982-02-12 1983-02-10 Bildwiederholspeicher-Architektur mit schnellem Zugriff für eine graphische Anzeigeeinrichtung

Publications (1)

Publication Number Publication Date
ATE36425T1 true ATE36425T1 (de) 1988-08-15

Family

ID=23368372

Family Applications (1)

Application Number Title Priority Date Filing Date
AT83300657T ATE36425T1 (de) 1982-02-12 1983-02-10 Bildwiederholspeicher-architektur mit schnellem zugriff fuer eine graphische anzeigeeinrichtung.

Country Status (7)

Country Link
US (1) US4546451A (de)
EP (1) EP0087868B1 (de)
JP (1) JPS58147789A (de)
AT (1) ATE36425T1 (de)
CA (1) CA1208820A (de)
DE (1) DE3377682D1 (de)
IE (1) IE830288L (de)

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USRE35680E (en) * 1988-11-29 1997-12-02 Matsushita Electric Industrial Co., Ltd. Dynamic video RAM incorporating on chip vector/image mode line modification
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US5148523A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporationg on chip line modification
US5142637A (en) * 1988-11-29 1992-08-25 Solbourne Computer, Inc. Dynamic video RAM incorporating single clock random port control
JP2708841B2 (ja) * 1989-01-11 1998-02-04 富士通株式会社 ビットマップメモリの書き込み方法
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US5317706A (en) * 1989-11-15 1994-05-31 Ncr Corporation Memory expansion method and apparatus in a virtual memory system
US5361387A (en) * 1990-10-09 1994-11-01 Radius Inc. Video accelerator and method using system RAM
US5210723A (en) * 1990-10-31 1993-05-11 International Business Machines Corporation Memory with page mode
US5274786A (en) * 1990-11-28 1993-12-28 Hewlett-Packard Company Microprocessor memory bus interface for inhibiting relatching of row address portions upon subsequent accesses including a same row address portion
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WO1993004429A2 (en) * 1991-08-13 1993-03-04 Board Of Regents Of The University Of Washington Method of generating multidimensional addresses in an imaging and graphics processing system
WO1993004461A1 (en) * 1991-08-15 1993-03-04 Metheus Corporation High speed ramdac with reconfigurable color palette
US5321809A (en) * 1992-09-11 1994-06-14 International Business Machines Corporation Categorized pixel variable buffering and processing for a graphics system
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging
US5815646A (en) * 1993-04-13 1998-09-29 C-Cube Microsystems Decompression processor for video applications
US5809174A (en) * 1993-04-13 1998-09-15 C-Cube Microsystems Decompression processor for video applications
JPH09506439A (ja) * 1993-10-29 1997-06-24 サン・マイクロシステムズ・インコーポレーテッド 行アドレス・ストローブ・サイクルを必要としないでフレーム・バッファ動作を行う方法と装置
US5422998A (en) * 1993-11-15 1995-06-06 Margolin; Jed Video memory with flash fill
US5671377A (en) * 1994-07-19 1997-09-23 David Sarnoff Research Center, Inc. System for supplying streams of data to multiple users by distributing a data stream to multiple processors and enabling each user to manipulate supplied data stream
US5815168A (en) * 1995-06-23 1998-09-29 Cirrus Logic, Inc. Tiled memory addressing with programmable tile dimensions
US5704059A (en) * 1995-07-28 1997-12-30 Nec Corporation Method of write to graphic memory where memory cells designated by plurality of addresses selected simultaneously for one row address are written
US5909658A (en) * 1996-06-18 1999-06-01 International Business Machines Corporation High speed electron beam lithography pattern processing system
US5999199A (en) * 1997-11-12 1999-12-07 Cirrus Logic, Inc. Non-sequential fetch and store of XY pixel data in a graphics processor
US6031550A (en) * 1997-11-12 2000-02-29 Cirrus Logic, Inc. Pixel data X striping in a graphics processor
US5982397A (en) * 1997-11-14 1999-11-09 Philips Electronics North America Corporation Video graphics controller having locked and unlocked modes of operation
US6674443B1 (en) 1999-12-30 2004-01-06 Stmicroelectronics, Inc. Memory system for accelerating graphics operations within an electronic device
GB0103736D0 (en) * 2001-02-15 2001-04-04 Hewlett Packard Co Transmission controls on data communication such as E-mail
EP1568036B1 (de) * 2002-11-20 2008-08-27 Nxp B.V. Sdram adressenabbildung optimiert für zwei-dimensionalen zugriff
JP2004222611A (ja) * 2003-01-23 2004-08-12 Shimano Inc 両軸受リールのレベルワインド機構
US7280428B2 (en) * 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
TWI391912B (zh) * 2008-11-14 2013-04-01 Orise Technology Co Ltd 圖框記憶體存取方法以及使用其之顯示驅動器

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Also Published As

Publication number Publication date
JPS58147789A (ja) 1983-09-02
EP0087868A2 (de) 1983-09-07
EP0087868A3 (en) 1984-12-27
CA1208820A (en) 1986-07-29
EP0087868B1 (de) 1988-08-10
DE3377682D1 (en) 1988-09-15
US4546451A (en) 1985-10-08
IE830288L (en) 1983-08-12

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