ATE341027T1 - Multiprozessorsystem und verfahren zum betrieb eines multiprozessorsystems - Google Patents

Multiprozessorsystem und verfahren zum betrieb eines multiprozessorsystems

Info

Publication number
ATE341027T1
ATE341027T1 AT02735883T AT02735883T ATE341027T1 AT E341027 T1 ATE341027 T1 AT E341027T1 AT 02735883 T AT02735883 T AT 02735883T AT 02735883 T AT02735883 T AT 02735883T AT E341027 T1 ATE341027 T1 AT E341027T1
Authority
AT
Austria
Prior art keywords
processor
tokens
results
indication
command
Prior art date
Application number
AT02735883T
Other languages
English (en)
Inventor
I-Chih Kang
Om P Gangwal
Andre K Nieuwland
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE341027T1 publication Critical patent/ATE341027T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Advance Control (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
AT02735883T 2001-06-29 2002-06-20 Multiprozessorsystem und verfahren zum betrieb eines multiprozessorsystems ATE341027T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01202517 2001-06-29

Publications (1)

Publication Number Publication Date
ATE341027T1 true ATE341027T1 (de) 2006-10-15

Family

ID=8180570

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02735883T ATE341027T1 (de) 2001-06-29 2002-06-20 Multiprozessorsystem und verfahren zum betrieb eines multiprozessorsystems

Country Status (7)

Country Link
US (2) US20040193693A1 (de)
EP (3) EP1421506A2 (de)
JP (3) JP2004534323A (de)
CN (3) CN1531684A (de)
AT (1) ATE341027T1 (de)
DE (1) DE60215007T2 (de)
WO (3) WO2003005219A2 (de)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7293155B2 (en) * 2003-05-30 2007-11-06 Intel Corporation Management of access to data from memory
TW587374B (en) * 2003-06-03 2004-05-11 Acer Labs Inc Method and related apparatus for generating high frequency signals by a plurality of low frequency signals with multiple phases
US7714870B2 (en) * 2003-06-23 2010-05-11 Intel Corporation Apparatus and method for selectable hardware accelerators in a data driven architecture
US7546423B2 (en) * 2003-09-02 2009-06-09 Sirf Technology, Inc. Signal processing system control method and apparatus
DE102004051952A1 (de) * 2004-10-25 2006-04-27 Robert Bosch Gmbh Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem
US7590777B2 (en) * 2004-12-10 2009-09-15 International Business Machines Corporation Transferring data between system and storage in a shared buffer
JP4148223B2 (ja) * 2005-01-28 2008-09-10 セイコーエプソン株式会社 プロセッサおよび情報処理方法
US20060253662A1 (en) * 2005-05-03 2006-11-09 Bass Brian M Retry cancellation mechanism to enhance system performance
US8817029B2 (en) * 2005-10-26 2014-08-26 Via Technologies, Inc. GPU pipeline synchronization and control system and method
US20080052527A1 (en) * 2006-08-28 2008-02-28 National Biometric Security Project method and system for authenticating and validating identities based on multi-modal biometric templates and special codes in a substantially anonymous process
US7958182B2 (en) 2007-08-27 2011-06-07 International Business Machines Corporation Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture
US8108545B2 (en) 2007-08-27 2012-01-31 International Business Machines Corporation Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture
US7904590B2 (en) 2007-08-27 2011-03-08 International Business Machines Corporation Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture
US8014387B2 (en) 2007-08-27 2011-09-06 International Business Machines Corporation Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture
US7793158B2 (en) 2007-08-27 2010-09-07 International Business Machines Corporation Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture
US7822889B2 (en) 2007-08-27 2010-10-26 International Business Machines Corporation Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture
US7769891B2 (en) 2007-08-27 2010-08-03 International Business Machines Corporation System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture
US7840703B2 (en) 2007-08-27 2010-11-23 International Business Machines Corporation System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture
US8185896B2 (en) * 2007-08-27 2012-05-22 International Business Machines Corporation Method for data processing using a multi-tiered full-graph interconnect architecture
US8140731B2 (en) 2007-08-27 2012-03-20 International Business Machines Corporation System for data processing using a multi-tiered full-graph interconnect architecture
US7809970B2 (en) 2007-08-27 2010-10-05 International Business Machines Corporation System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture
US7769892B2 (en) 2007-08-27 2010-08-03 International Business Machines Corporation System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture
US7958183B2 (en) 2007-08-27 2011-06-07 International Business Machines Corporation Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture
US7827428B2 (en) 2007-08-31 2010-11-02 International Business Machines Corporation System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture
US7921316B2 (en) 2007-09-11 2011-04-05 International Business Machines Corporation Cluster-wide system clock in a multi-tiered full-graph interconnect architecture
US7779148B2 (en) 2008-02-01 2010-08-17 International Business Machines Corporation Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips
US20090198956A1 (en) * 2008-02-01 2009-08-06 Arimilli Lakshminarayana B System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture
US8077602B2 (en) 2008-02-01 2011-12-13 International Business Machines Corporation Performing dynamic request routing based on broadcast queue depths
DE102008018951A1 (de) 2008-04-15 2009-10-22 Carl Zeiss Microimaging Gmbh Mikroskop mit Haltefokuseinheit
US8082426B2 (en) * 2008-11-06 2011-12-20 Via Technologies, Inc. Support of a plurality of graphic processing units
US8843682B2 (en) * 2010-05-18 2014-09-23 Lsi Corporation Hybrid address mutex mechanism for memory accesses in a network processor
US8417778B2 (en) 2009-12-17 2013-04-09 International Business Machines Corporation Collective acceleration unit tree flow control and retransmit
US8689240B2 (en) 2011-06-10 2014-04-01 International Business Machines Corporation Transmitting operator message commands to a coupling facility
US9037907B2 (en) * 2011-06-10 2015-05-19 International Business Machines Corporation Operator message commands for testing a coupling facility
US8918797B2 (en) 2011-06-10 2014-12-23 International Business Machines Corporation Processing operator message commands
US8560737B2 (en) 2011-06-10 2013-10-15 International Business Machines Corporation Managing operator message buffers in a coupling facility
US8799522B2 (en) 2011-06-10 2014-08-05 International Business Machines Corporation Executing a start operator message command
US8745291B2 (en) 2011-10-04 2014-06-03 Qualcomm Incorporated Inter-processor communication apparatus and method
CN103186501A (zh) * 2011-12-29 2013-07-03 中兴通讯股份有限公司 一种多处理器共享存储方法及系统
US9304880B2 (en) * 2013-03-15 2016-04-05 Freescale Semiconductor, Inc. System and method for multicore processing
US9928117B2 (en) * 2015-12-11 2018-03-27 Vivante Corporation Hardware access counters and event generation for coordinating multithreaded processing
US10437748B1 (en) * 2015-12-29 2019-10-08 Amazon Technologies, Inc. Core-to-core communication
US10042677B2 (en) * 2016-05-25 2018-08-07 Bank Of America Corporation Maintenance conflict tool
US10963183B2 (en) * 2017-03-20 2021-03-30 Intel Corporation Technologies for fine-grained completion tracking of memory buffer accesses
CN107342853B (zh) * 2017-05-25 2019-12-06 兴唐通信科技有限公司 一种低交互开销的计数器同步方法
CN110502330A (zh) 2018-05-16 2019-11-26 上海寒武纪信息科技有限公司 处理器及处理方法
CN109117415B (zh) * 2017-06-26 2024-05-14 上海寒武纪信息科技有限公司 数据共享系统及其数据共享方法
CN110413551B (zh) 2018-04-28 2021-12-10 上海寒武纪信息科技有限公司 信息处理装置、方法及设备
CN109214616B (zh) 2017-06-29 2023-04-07 上海寒武纪信息科技有限公司 一种信息处理装置、系统和方法
WO2019001418A1 (zh) 2017-06-26 2019-01-03 上海寒武纪信息科技有限公司 数据共享系统及其数据共享方法
CN109426553A (zh) 2017-08-21 2019-03-05 上海寒武纪信息科技有限公司 任务切分装置及方法、任务处理装置及方法、多核处理器
JP7407653B2 (ja) * 2020-04-27 2024-01-04 株式会社平和 遊技機
US11842056B2 (en) * 2021-10-25 2023-12-12 EMC IP Holding Company, LLC System and method for allocating storage system resources during write throttling

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916658A (en) * 1987-12-18 1990-04-10 International Business Machines Corporation Dynamic buffer control
US5584037A (en) * 1994-03-01 1996-12-10 Intel Corporation Entry allocation in a circular buffer
EP0760501B1 (de) * 1995-09-04 2002-02-20 Hewlett-Packard Company, A Delaware Corporation Dataverarbeitungssystem mit ringförmiger Warteschlange in einem Seitenspeicher
US5729765A (en) * 1995-12-07 1998-03-17 Samsung Electronics Co., Ltd. Method and apparatus for determining the status of a shared resource
US5951657A (en) * 1996-06-19 1999-09-14 Wisconsin Alumni Research Foundation Cacheable interface control registers for high speed data transfer
US5915128A (en) * 1997-01-29 1999-06-22 Unisys Corporation Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register
US6173307B1 (en) * 1998-08-20 2001-01-09 Intel Corporation Multiple-reader multiple-writer queue for a computer system
US6212543B1 (en) * 1998-12-10 2001-04-03 Intel Corporation Asymmetric write-only message queuing architecture
US6389489B1 (en) * 1999-03-17 2002-05-14 Motorola, Inc. Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size
US6606666B1 (en) * 1999-11-09 2003-08-12 International Business Machines Corporation Method and system for controlling information flow between a producer and a buffer in a high frequency digital system
ATE302969T1 (de) * 2000-08-17 2005-09-15 Texas Instruments Inc Unterhaltung einer entfernten warteschlange unter benutzung von zwei zählern in der verschiebesteuerung mit hubs und ports
US6424189B1 (en) * 2000-10-13 2002-07-23 Silicon Integrated Systems Corporation Apparatus and system for multi-stage event synchronization
KR100484134B1 (ko) * 2002-02-16 2005-04-18 삼성전자주식회사 선입선출기를 이용한 비동기 데이터 인터페이스 장치

Also Published As

Publication number Publication date
WO2003005196A2 (en) 2003-01-16
CN1522402A (zh) 2004-08-18
DE60215007T2 (de) 2007-05-03
EP1405184A2 (de) 2004-04-07
WO2003005196A3 (en) 2004-01-15
WO2003003232A3 (en) 2004-03-18
WO2003005219A3 (en) 2003-06-05
CN1531684A (zh) 2004-09-22
JP2004534323A (ja) 2004-11-11
WO2003005219A2 (en) 2003-01-16
EP1421506A2 (de) 2004-05-26
CN100533370C (zh) 2009-08-26
EP1405175A2 (de) 2004-04-07
DE60215007D1 (de) 2006-11-09
JP2004531002A (ja) 2004-10-07
EP1405175B1 (de) 2006-09-27
US20040153524A1 (en) 2004-08-05
CN1522405A (zh) 2004-08-18
WO2003003232A2 (en) 2003-01-09
US20040193693A1 (en) 2004-09-30
JP2004522233A (ja) 2004-07-22

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