US6389489B1 - Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size - Google Patents
Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size Download PDFInfo
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- US6389489B1 US6389489B1 US09/271,215 US27121599A US6389489B1 US 6389489 B1 US6389489 B1 US 6389489B1 US 27121599 A US27121599 A US 27121599A US 6389489 B1 US6389489 B1 US 6389489B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
- G06F2205/108—Reading or writing the data blockwise, e.g. using an extra end-of-block pointer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
- G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
Definitions
- This invention relates generally to data processing systems and more particularly to data buffering in a data processing system.
- FIFO first-in, first-out
- Certain FIFOs contain threshold values that serve to control their operation. For instance, a threshold might be set to generate an interrupt to the data source if the source is about to exceed the capacity of the FIFO (overrun). Conversely, a threshold might be set to disable the output of data until an uninterrupted supply of data can be guaranteed (underrun).
- Some communications protocols specify fixed length transmissions of blocks, or packets, of data. If one or more gaps are interjected into the transmission because of, for example, an underrun or overrun, then one or more data beats at the end of the transmission may be ignored by the destination to ensure that an output data stream is transmitted without interruption and contains no bubbles or gaps.
- FIG. 1 illustrates, in block diagram form, a data processing system in which the disclosed invention may be incorporated
- FIG. 2 illustrates, in block diagram form, a FIFO depicted in FIG. 1 constructed in accordance with the present invention
- FIG. 3 illustrates, in graphical form, a DATA/CONTROL ENTRY depicted in FIG. 2 .
- FIG. 1 illustrates, in block diagram form, a data processing system 100 in which the disclosed invention may be incorporated.
- Devices in data processing system 100 communicate with each other using a high-speed bus protocol. Each device can operate at its own clock rate. According to this protocol, data to be transmitted between devices is grouped into packets by the device generating the data (data producer or source), buffered in FIFOs, and automatically transmitted to a receiving device (data consumer or destination). Control or “header” information is embedded into the packet and is used to indicate such things as the destination of the packet, its length, etc.
- a first data processor 102 communicates with a second data processor 104 via two uni-directional communication buses.
- Data processor 104 may be able to consume data at a rate greater than the rate at which data processor 102 can produce data. However, data processor 104 cannot interrupt the transmission of a packet to wait for additional data. Therefore, data processor 102 uses a FIFO buffer to buffer a certain fraction of the packet before it begins transmitting the data to data processor 104 .
- the minimum amount of data temporarily stored in the FIFO buffer depends upon the rate at which data processor 102 produces data, the rate at which data processor 104 consumes data, and the size of the packet.
- variable threshold information is stored in the FIFO along with data. The FIFO uses the threshold information as a predetermined maximum fullness value of the FIFO buffer.
- a data block, or packet can be transmitted to the second device from the FIFO buffer without risk of introducing bubbles into an individual data packet.
- the data packet is transmitted as an uninterrupted data stream.
- the threshold value is automatically determined by the transmitting data processor on a per-packet basis to maximize data throughput.
- the transmitting data processor determines the variable threshold value as a function of a difference between an input data rate and an output data rate of the FIFO buffer, and a size of the data block to be transmitted through the FIFO buffer.
- the calculated threshold value is then appended to a first entry of the data block. Specifically, start-up latency is tailored to the size of each packet.
- shorter packets can be completely loaded into the FIFO faster than longer packets.
- the shorter packets can have lower thresholds. This strategy may cause the FIFO to begin transmitting the shorter packet, as an unbroken data stream, earlier than if it had the threshold appropriate for the longer packet.
- data processor 102 includes a central processing unit 106 (CPU 1 ) and a bus interface unit 108 .
- Bus interface unit 108 includes an output FIFO buffer 110 and an input FIFO buffer 112 .
- data processor 104 includes a central processing unit 114 (CPU 2 ) and a bus interface unit 116 .
- Bus interface unit 116 includes an output FIFO buffer 118 and an input FIFO buffer 120 .
- the output FIFO buffer 110 is connected to the input FIFO buffer 120 .
- the output FIFO buffer 118 is connected to the input FIFO buffer 112 .
- data processor 102 is implemented on a separate integrated circuit than data processor 104 .
- CPU 1 executes instructions stored in memory (not depicted) using operands also stored in memory and received from an external source (not shown).
- Bus interface unit 110 coordinates communications from CPU 1 to other devices in the data processing system and vice versa.
- FIFOs 110 and 112 buffer data so that CPU 1 can perform other work while extended communications are in operation.
- FIFO 110 is described below in connection with FIG. 2 .
- CPU 2 operates similarly.
- the depicted embodiment illustrates a data processing system in which two data processors are connected directly to each other.
- data processor 104 may be replaced with a volatile memory system, with a non-volatile memory system, with one or more user input devices such as a keyboard or monitor, with a bus-to-bus interconnect, etc.
- the single point-to-point topology depicted in FIG. 1 may be replaced with topologies that contain more than one possible data destination.
- data processor 102 may be installed in a ring topology in which messages are passed from device to device until a packet reaches its destination or returns to the data producer.
- data processor 102 may be connected to a switched network topology in which a message is routed to a destination by an intermediate device connected to the data producer and to several data consumers.
- FIG. 2 illustrates, in block diagram form, FIFO 110 depicted in FIG. 1 constructed in accordance with the present invention.
- FIFO 110 contains twenty DATA/CONTROL ENTRIES 200 .
- Each one of the entries contains eight CONTROL bits and sixty-eight DATA bits.
- the sixty-eight DATA bits are further divided into four seventeen bit sections.
- the input of each entry is connected to a data producer via DATA IN.
- DATA IN includes both the data and control bits for each entry.
- the output of each entry is connected to a data consumer via a 20:1 multiplexer (MUX) 202 and a 5:1 MUX 204 .
- MUX multiplexer
- a multi-bit control signal labeled READ POINTER selects which of the twenty inputs to MUX 202 is output to MUX 204 .
- An output of MUX 202 provides a set of sixty-eight DATA bits from a selected entry to MUX 204 .
- the first section of seventeen DATA bits output by MUX 202 are connected to the first input of MUX 204 .
- the second section of seventeen DATA bits output by MUX 202 are connected to the second input of MUX 204 .
- the third section of seventeen DATA bits output by MUX 202 are connected to the third input of MUX 204 .
- the fourth section of seventeen DATA bits output by MUX 202 are connected to the fourth input of MUX 204 .
- a default output labeled NOP is connected to the fifth input of MUX 204 .
- the output of a MUX controller 206 selects which of the five inputs to MUX 204 is output to CPU 2 as DATA OUT. Note that the number of entries and the number of control bits and data bits per entry are provided for illustration purposes only and may be different in other embodiments.
- MUX 202 also outputs a selected set of eight CONTROL bits to a read comparator 210 .
- Read comparator 210 receives the control signal labeled READ POINTER and a multi-bit control signal labeled WRITE POINTER, each synchronized by a pair of serially connected latches, 214 and 218 , respectively.
- Read comparator 210 generates a control signal START ⁇ overscore (STOP) ⁇ .
- the control signal START ⁇ overscore (STOP) ⁇ is connected to a read counter 208 and to MUX controller 206 .
- Read counter 208 generates the control signal READ POINTER.
- a write counter 212 generates the control signal WRITE POINTER.
- Write counter 212 also encodes the control signal WRITE POINTER into a one-of-N format. A differing one of each of the N output signals is connected to a differing one of the DATA CONTROL ENTRIES 200 .
- Write counter 212 receives a multi-bit control signal WRITE CONTROL from the data producer.
- the data producer is CPU 1 .
- a write comparator 216 receives the control signal READ POINTER synchronized by a pair of serially connected latches 218 , receives the control signal WRITE POINTER, and generates a control signal labeled READY. The control signal READY is provided to the data producer.
- FIFO 110 Although the various blocks within FIFO 110 are integrated into a single electronic circuit, certain portions operate at different clock speeds. This differentiation enables the exchange of data between the data producer and FIFO 110 and enables the exchange of data between FIFO 110 and the data consumer.
- the data consumer operates at a higher clock rate than does the data producer.
- MUX 204 , MUX controller 206 , read counter 208 , read comparator 210 , and latch pair 214 operate in the data consumer's time domain.
- DATA/CONTROL ENTRIES 200 , MUX 202 , write counter 212 , write comparator 216 , and latch pair 218 operate in the data producer's time domain. Note that in other embodiments, the data rate of the data consumer may be lower than the data rate of the data producer, or may even have the same data rate as the producer.
- FIFO 110 may be conveniently described with respect to its two major functions: writing data and reading data. After a reset or initialization operation, the write counter 212 and read counter 208 are set to the same initial value. Also, MUX controller 206 selects the fifth, or NOP, input of MUX 204 as its output.
- write comparator 216 After reset, write comparator 216 will detect that the read and write pointers are equivalent. This equivalency indicates that no valid data is in FIFO 110 , and that all entries are available for receiving data. At other times, the write pointer may lag the read pointer by more than one location. In these cases, there is at least one location in which to store data. In each of these circumstances, write comparator 216 will assert the control signal READY to the data producer indicating the ability of the FIFO to store data. At other times, FIFO 110 may become full. In this case, the write pointer will catch up to the read pointer. To avoid over-writing valid data, write comparator 216 will de-assert READY.
- the data producer will be required to write data in FIFO 110 .
- the data producer will input data to FIFO 110 via the data input DATA IN and will assert certain ones of control signals WRITE CONTROL, indicating valid data.
- Write counter 212 will enable one entry within FIFO 110 to store the data by asserting its single-bit output corresponding to the entry. Write counter 212 will also increment itself to ensure that previously stored data is not over-written at a later time.
- each packet begins at the first bit position in the first section of the entry.
- the end of the data packet can be located in any of the four sections of an entry.
- each packet may occupy more than or less than a single entry, or a packet may be larger than the FIFO can store at once.
- Five of the eight control bits reflect a threshold value.
- FIFO 110 will not begin transmission of a packet until at least R entries are filled.
- T is the number of FIFO entries required to store the entire packet
- f c is the clock frequency of the data consumer
- f p is the clock frequency of the data producer.
- the function INT conventionally rounds its input to an integer.
- the data producer calculates R for each packet it buffers in FIFO 110 and includes the threshold value in the packet data stream to be stored in the threshold value bit field of the control bit section of an entry along with start bits to indicate a beginning of a data packet.
- Equation 1 is not the only way to calculate the threshold value and other equations may be used in other embodiments depending upon factors such as available hardware and the particular application.
- FIG. 3 illustrates the bit fields of an entry, and will be discussed later. Note that the CPU of the data producer may be used to determine the threshold value using Equation 1, or a dedicated co-processor may be used in order to reduce the work load of the CPU.
- MUX controller 206 and read comparator 210 attempt to output data to the data consumer as soon as possible.
- MUX controller 206 selects the default output NOP as the output of MUX 204 .
- the first condition in which MUX 204 outputs NOP is when there is no buffered data to output.
- read comparator 210 detects that the read and write pointers are equivalent, and de-asserts the control signal START ⁇ overscore (STOP) ⁇ .
- START ⁇ overscore (STOP) ⁇ The second condition in which MUX 204 outputs NOP is when there is buffered data but less than the amount specified in the threshold control field.
- read comparator 210 receives the calculated threshold field output by MUX 202 and compares it with the difference between the read and write pointers. If the difference is less than the threshold value, then read comparator 210 will de-assert the control signal START ⁇ overscore (STOP) ⁇ to stop the data flow to the consumer.
- START overscore
- write counter 212 increments its output WRITE POINTER. Eventually, the data producer will buffer enough information to begin outputting data to the data consumer.
- Read comparator 210 will detect this condition when the difference between the read and write pointers is equal to or greater than the stored threshold value. Read comparator 210 asserts the control signal START ⁇ overscore (STOP) ⁇ .
- STOP control signal START ⁇ overscore
- MUX controller 206 selects the first input to MUX 204 as its output. MUX controller 206 will cycle through its first through fourth inputs synchronously with the data consumer time domain clock.
- Read counter 208 increments its output READ POINTER after four consumer domain clock cycles.
- the READ POINTER indicates which DATA/CONTROL ENTRY is output by MUX 202 .
- MUX controller 206 and read comparator 210 will continue outputting each successive entry until the packet is completely output to the data consumer.
- Read comparator 210 detects the end of each packet by a particular CONTROL bit field.
- Read comparator 210 will perform a new comparison between the read pointer, write pointer, and threshold field for the next packet. If the data packet is larger than the FIFO buffer can store at one time, write operations to the FIFO buffer will overlap in time with the read operations to ensure that a continuous data stream is transmitted to the data consumer.
- each of the different sized data blocks can transmitted through the first-in, first-out buffer without interruption from the producer of the data to the consumer of the data.
- FIG. 3 illustrates, in graphical form, a DATA/CONTROL ENTRY depicted in FIG. 2 .
- the first and second bits comprise a START field to indicate when to start transferring data to the FIFO buffer. All entries associated with a single packet except the last entry are encoded with the pattern 00. The last entry in a packet is encoded with the pattern 11 to indicate stop transferring data. This bit pattern indicates to read comparator 210 to perform another comparison.
- the third through seventh bits comprise the THRESHOLD field. At least the first entry in each packet contains a value corresponding to the number of entries required before beginning data transmission.
- the control bits used to indicate START also indicate that a corresponding variable threshold value is valid. The subsequent entries may or may not contain the threshold value.
- each entry in FIFO 110 may contain one or more instructions for execution by a data processor or by execution units in a data processor.
- the disclosed invention could be used to initiate sequential execution of instructions in an instruction stack of a data processing system without the problem of gaps between the instructions. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.
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Cited By (80)
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US20020077981A1 (en) * | 2000-11-13 | 2002-06-20 | Yozan, Inc. | Communication terminal device and billing device |
US7974247B2 (en) * | 2000-11-13 | 2011-07-05 | Daita Frontier Fund, Llc | Communication terminal device and billing device |
US7581043B2 (en) * | 2000-11-15 | 2009-08-25 | Seagate Technology Llc | Dynamic buffer size allocation for multiplexed streaming |
US20060080482A1 (en) * | 2000-11-15 | 2006-04-13 | Seagate Technology Llc | Dynamic buffer size allocation for multiplexed streaming |
US6754743B2 (en) * | 2001-01-04 | 2004-06-22 | Lucent Technologies Inc. | Virtual insertion of cells from a secondary source into a FIFO |
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