US20040098509A1 - System for reordering sequenced based packet segments in a switching network - Google Patents

System for reordering sequenced based packet segments in a switching network Download PDF

Info

Publication number
US20040098509A1
US20040098509A1 US10/295,399 US29539902A US2004098509A1 US 20040098509 A1 US20040098509 A1 US 20040098509A1 US 29539902 A US29539902 A US 29539902A US 2004098509 A1 US2004098509 A1 US 2004098509A1
Authority
US
United States
Prior art keywords
memory
packet segments
segment
segments
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/295,399
Inventor
Vic Alfano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TOPSIDE RESEARCH LLC
Original Assignee
Internet Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Internet Machines Corp filed Critical Internet Machines Corp
Priority to US10/295,399 priority Critical patent/US20040098509A1/en
Assigned to INTERNET MACHINES CORPORATION reassignment INTERNET MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ALFANO, VIC
Publication of US20040098509A1 publication Critical patent/US20040098509A1/en
Assigned to TOPSIDE RESEARCH, LLC reassignment TOPSIDE RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNET MACHINES CORP.
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • H04L47/34Sequence integrity, e.g. sequence numbers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Application independent communication protocol aspects or techniques in packet data networks
    • H04L69/14Multichannel or multilink protocols
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Application independent communication protocol aspects or techniques in packet data networks
    • H04L69/22Header parsing or analysis

Abstract

System for reordering packet segments in a switching network. A system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. A memory and map logic located at the destination processor operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. A Dequeue processor coupled to the memory operates to determine when enough packet segments are stored in the memory to form a complete data frame and outputs that frame.

Description

    FIELD OF THE INVENTION
  • The present invention is related generally to the operation of switching networks, and more particularly, to a system for reordering sequence based packet segments in a switching network. [0001]
  • BACKGROUND OF THE INVENTION
  • Communications networks now require the handling of data at very high data rates. For example, 10 gigabits per second (Gbps) is common. When it is required to process data at these speeds, multiple high-speed parallel connections may be used to increase the effective bandwidth. However, this may result in one or more transmission problems, since the data streams must be divided to be distributed over the multiple parallel connections, and at some point after parallel transmission, recombined to form the original streams. [0002]
  • FIG. 1 shows a block diagram [0003] 100 of a typical network structure for transmitting data frames (or data packets) from source processors 102 to a destination processor 104 via network fabrics 106. The data streams include frames that may comprise a fixed amount of data. For example, stream A may include frames A0, A1, and A2 that are received by the source processor A and transmitted to each of the fabrics as shown. The stream B may include frames B0, B1 and B2 that are transmitted to the fabrics by source processor B as shown, and the stream C may include frames C0, C1 and C2 that are transmitted to the fabrics by source processor C as shown.
  • Once the frames are received by the fabrics, they are transmitted to the destination processor [0004] 104. The destination processor receives the frames in the order they arrive and combines them for transmission to another network entity, as shown by stream D.
  • A significant problem that exists with current transmission systems, such as the system shown in FIG. 1, is that the frames may end up in the wrong order when transmitted from the destination processor D. For example, the frames may be output in the order shown at [0005] 108. In this case, frame B2 is output before frame B1, and frame C2 is output before frame C1. Thus, the frames received from source processors B and C are transmitted from the destination processor 104 out of order. In such a case, it may be necessary to discard the out of order frames of data and request a new transmission of those frames. As a result, additional overhead will be used and a corresponding loss of transmission bandwidth will be realized.
  • Additional problems can occur in systems where the transmitted data frames have been segmented before transmission. In these systems, it is possible that both the frames and/or individual segments of each frame are transmitted out of order. Thus, even if the frames maintain the correct order with respect to a transmitting source processor, segments within the frames may be out of order. [0006]
  • Therefore, it would be desirable to have a way to reorder frames of data in a transmission system so that the frames are output in the correct order, thereby improving transmission efficiency. Furthermore, it would also be desirable to have a way to reorder frame segments so that both the frames and their corresponding segments are output in the correct order. [0007]
  • SUMMARY OF INVENTION
  • The present invention includes a system for reordering sequenced based packet segments in a switching network. For example, in one embodiment of the invention, a reordering system is provided that receives packet segments from multiple sources and reorders the received packet segments based on sequence information associated with each segment so that both the segments, and frames constructed from the segments, are output from a destination processor in the correct order. [0008]
  • In one embodiment included in the present invention, a system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. The system also comprises a memory and map logic located at the destination processor that operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. The system also comprises a Dequeue processor coupled to the memory and operable to determine when enough packet segments are stored in the memory to form a complete data frame. When enough packets are received, the Dequeue processor operates to output the packet segments that form the complete data frame. [0009]
  • In another embodiment included in the present invention, a method is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The method comprises steps of: including a segment identifier with each of the packet segments before they are transmitted from the source processors; defining one or more memory regions in a memory located at the destination processor; mapping the segment identifier associated with each received packet segment to a selected memory region, wherein the received packet segment is stored at the selected memory region; updating a memory map; identifying when enough packet segments have been received to form a complete data frame; and outputting the complete data frame.[0010]
  • BRIEF DESCRIPTION OF DRAWINGS
  • The foregoing aspects and the attendant advantages of this invention will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein: [0011]
  • FIG. 1 shows a block diagram of a typical network structure for transmitting data frames from source processors to destination processors; [0012]
  • FIG. 2 shows a diagram showing one embodiment of a system for reordering segments constructed in accordance with the present invention; [0013]
  • FIG. 3 shows a diagram of one embodiment of a segment encoder for use in a source processor; [0014]
  • FIG. 4 shows a diagram of one embodiment of a reordering system constructed in accordance with the present invention; [0015]
  • FIG. 5 shows one embodiment of a memory for use in the reordering system of FIG. 4; [0016]
  • FIG. 6 shows a diagram of one embodiment of a mapping system for use in the reordering system of FIG. 4; [0017]
  • FIG. 7 shows one embodiment of a memory map for use in the reordering system of FIG. 4; and [0018]
  • FIG. 8 shows a flow diagram for reordering segments in accordance with the present invention.[0019]
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
  • The present invention includes a system for reordering sequenced based packet segments in a switching network. For example, in one embodiment of the invention, a reordering system is provided that receives packet segments from multiple sources and reorders the received packet segments based on the transmitting source, a sequence number, and a priority level associated with each segment. Thus, various embodiments of the system included in the present invention are discussed in detail in the following text. [0020]
  • Exemplary Embodiment [0021]
  • FIG. 2 shows a diagram of one embodiment of a reordering system [0022] 200 constructed in accordance with the present invention for reordering packet segments in a switching network. The system 200 includes source processors 204 that each include a segment encoder 202 that operates to segment data frames included in the streams received by each source processor, and encode each segment in accordance with the present invention.
  • During operation of the system [0023] 200, the source processors 204 receive data streams containing data frames. The segment encoders 202 operate to segment each of the data frames into packet segments and encode a unique sequence identifier for each segment prior to transmitting them to one or more fabrics 206. In one embodiment of the invention, the segment encoders 202 also assign a priority to each segment in addition to the sequence identifier. Thus, each segment that is transmitted to the fabrics 210 includes a sequence identifier, and optionally, priority information. Furthermore, an identifier that identifies the transmitting source processor is included with each segment. The addition of the source identifier to the segments may be part of the operation of the source processors 204, or may be part of the operation of the segment encoders 202.
  • Any technique can be used to include sequence identifiers and/or priority levels with the packet segments. For example, the segment encoders can encode sequential sequence numbers into header information included with each segment. The priority indicator can be selected from one of several priority levels and also encoded into segment header information. Thus, any suitable technique can be used within the scope of the invention to associate a sequence identifier and priority information with each data segment. [0024]
  • The system [0025] 200 also includes a segment reordering system 208 at a destination processor 210. The reordering system 208 operates to receive the packet segments from the fabrics 206 and process the segments based on their respective sequence identifiers and priorities to reorder the segments, and thereby the frames, into the same order as when transmitted by the source processors. Thus, frames are reordered so that with respect to each source processor, the frames are placed in an identical order as when transmitted.
  • In FIG. 2, frames A, B, and C are transmitted from the source processors to the destination processor via the network fabrics. Each frame includes one or more segments that have been encoded with sequence numbers by the segment encoders associated with the source processors. Although FIG. 2 shows that each frame is transmitted to the destination via a selected network fabric, it is also possible that the segments within a frame are transmitted to the destination using multiple fabrics. Thus, the frames and corresponding segments may be transmitted to the destination using one or multiple fabrics, and the segment reordering system located at the destination will reorder the segments and frames to have the same order as when transmitted by their respective source processors. Therefore, the stream D includes all the frames in correct order, as shown at [0026] 212, and each frame includes segments that also have the correct order.
  • The destination processor may operate on the reordered data frames and segments in other ways to facilitate their transmission, but these other processes are not essential to the operation of one or more embodiments of the invention, and so will not be described in detailed. For example, the destination processor may serialize the frames for transmission, or provide known error detection and correction processes that are independent from the reordering system. [0027]
  • FIG. 3 shows a diagram of one embodiment of a segment encoder [0028] 202 constructed in accordance with the present invention, for use in a source processor 204. A source receiver 302 receives a data stream 304 that contains frames of data. The source receiver transfers the received stream to segmentation logic 306. The segmentation logic 306 segments the frames of data into frame or packet segments. For example, the data frames included in the stream are segmented into 64-byte segments.
  • The segmented frames are transferred to sequence and priority logic [0029] 308. The logic 308 operates to associate a sequence identifier with each of the segments it receives. For example, the sequence identifier may be a 10-bit sequence number and the segments are encoded with a consecutive sequence numbers. Furthermore, the logic 308 optionally operates to associate a priority indicator with each segment, where all segments within a frame are given the same priority level. For example, a 3-bit priority level indicator provides eight priority levels. However, any number of priority levels is suitable for use with the present invention.
  • Once the segments have been processed to include sequence identifiers, and optionally, a priority indicator, they are transferred to a source transmitter [0030] 310 where they are transmitted from the source processor to a destination processor via one or more network fabrics. As part of the transmission process, each segment will include a transmitting source identifier.
  • FIG. 4 shows a diagram of one embodiment of a segment reordering system [0031] 208 constructed in accordance with the present invention for use in a destination processor, for example, the destination processor 210 in FIG. 2.
  • The basic function of the segment reordering system [0032] 208 is to keep track of the order of all of the segments as they are received at the destination processor. In one or more embodiments, a combination of the source identifier, unique sequence number, and priority assigned to each segment and inserted into the segment header prior to transmission from the source processors are used to track the segments. At the reordering system, the transmitting source identifier and the priority will be used to sort and store the segments into one of 320 reorder queues (assuming 64 source processors and 5 priority levels). The unique sequence number, associated with a particular queue, will be used to index a segment into its proper location in a memory. The segment reordering system also reassembles the segments into frames before sending them on to a transmitter for transmission to other network entities.
  • A segment receiver [0033] 402 receives one or more data streams 412 that are transmitted to the destination processor via one or more network fabrics. For example, the receiver 402 receives the streams 412 via the fabrics 206. The receiver 402 is coupled to a memory 404 and segment processing logic 406. The segment processing logic 406 operates to process the source identifier, the sequence identifier, and the priority level associated with each segment to determine a free memory location in the memory 404 where each segment will be stored. The processing logic 406 also operates to update a memory map 414 that indicates used and unused portions of the memory 404. Another function of the processing logic is to update and maintain a set of pointers 418 that are used to indicate the segments that have been received. If there are enough received segments to form a complete frame, the complete frame is transmitted to another destination. The processing logic 406 may comprise any suitable hardware such as a CPU, gate array or other hardware logic, and may also include any suitable software to operate in conjunction with the hardware.
  • The memory [0034] 404 may comprise any suitable memory type or technology, such at RAM, DRAM or FLASH memory. Included in the memory 404 is the memory map 414 that is used to indicate used and unused portions of the memory. The memory map 414 allows the memory 404 to be efficiently utilized, and thus minimize the required total memory. The memory is designed to allow high-speed operation of the network fabrics. In one embodiment, the memory has a size of four megabytes (4M), however, larger or smaller memories may be used in accordance with the present invention. A more detailed discussion of the memory 404 and the memory map 414 is provided in another section of this document.
  • Segment Dequeue logic [0035] 408 is coupled to the memory 404 via control channel 422 and operates to control the output of reordered segments into reassembled frames. For example, in one embodiment, the Dequeue logic 408 operates to control the transfer of segments from the memory to the segment transmitter 410 based on block values it receives from the memory map 414 and the pointers 418. A communication channel 420 couples the Dequeue logic 408 with the segment processing logic 406 so that the Dequeue logic can access the pointers 418. The pointers 418 (FIG. 4) are used to provide an indication of the segments that have been received and stored in the memory 404. The pointers are also used to remove the segments from the memory to perform the reordering process and reassembly of frames. The pointers are updated as each received segment is stored in the memory 404. The Dequeue logic may comprise any suitable hardware such as a CPU, gate array or other hardware logic, and may also include any suitable software to operate in conjunction with the hardware.
  • A segment transmitter [0036] 410 receives segments transferred from the memory 404 by the Dequeue logic 408 and transmits these segments, and the reassembled frames they comprise, in the correct order to other entities in the network via a transmitter output 416. Thus, the reordering system 206 operates to perform reordering of segments and the reassembly of frames in accordance with the present invention.
  • FIG. 5 shows one embodiment of a memory structure [0037] 500 included in the memory 404 for use in a reordering system in accordance with the present invention. The memory structure 500 represents one memory structure, however, other memory structures are suitable for use in accordance with the present invention. Thus, FIG. 5 is exemplary and not intended to limit the scope of the invention to a particular memory structure.
  • The memory structure [0038] 500 includes a segment memory 502 coupled to a memory controller 504. The segment memory comprises a 64K portion of memory for each transmitting source. The 64K portion of memory is grouped into 16 blocks (0-15) with each block having the capacity to store 64 segments each having 64-bytes.
  • The memory controller [0039] 504 is coupled to all the 64K portions of memory so that segment data 506 may be stored and retrieved from any memory location based on a received memory address 508. The memory controller comprises any suitable hardware logic and/or associated software to access the memory 502.
  • In one embodiment, each memory portion comprises a total of 65536 (64K) bytes of storage that is dedicated to each transmitting source processor. If there are sixty-four source processors transmitting segment data, the memory [0040] 404 is sized to have a capacity of 4,194,304 bytes (4 Mbytes).
  • FIG. 6 shows a diagram of one embodiment of the memory map [0041] 414 that includes segment processing logic 650 and map tables 652 constructed in accordance with the present invention for use in the reordering system of FIG. 4. The segment processing logic 650 includes a segment decoder 603 that receives segment data from the segment receiver 402 and operates to decode sequence 604, priority 606, and transmitting source 608 information for each received segment. The sequence identifier 604, priority 606, and source identifier 608 are input to a map processor 602 that operates to output a memory address 508 that is formed from a portion of the sequence identifier 612, a memory block address 614 that is obtained from the map tables 652, and the source identifier 608. The map processor 602 also includes an interface 642 to the map tables 652. The map processor 602 may comprise any suitable hardware such as a CPU, gate array or other hardware logic, and may also include any suitable software that operates in conjunction with the hardware.
  • The map processor [0042] 602 is coupled to the memory tables 652 via a bus 618. The memory tables include a free list FIFO 620, a priority 0 table list 622, a priority 1 table list 624, a priority 2 table list 626, a priority 3 table list 628, and a priority 4 table list 630.
  • Associated with each priority table list is a valid list that contains valid bits. For example, the table list [0043] 622 is associated with valid list 632, the table list 624 is associated with valid list 634, the table list 626 is associated with valid list 636, the table list 628 is associated with valid list 638, and the table list 630 is associated with the valid list 640.
  • The group of memory lists are use to store the indirect location of the selected memory block [0044] 502 where the segment data is written. A set of these same lists exists for each source processor that is transmitting segment data to the destination. Therefore, if there are sixty-four source processors transmitting segment data, there will be sixty-four groups of memory lists. For example, as shown at 642, there are sixty-four bus connections that connect the map processor 602 to sixty-four groups of lists that are used to store segment data from sixty-four transmitting source processors. Although the memory lists shown are based on five priority levels, more or less priority levels may be used and result in a corresponding number of memory lists.
  • The map processor [0045] 602 operates to map segment data into the memory 404 for storage. The map processor uses the source identifier 608 to select which group of lists to use to map the segment data. For example, if the source identifier is twenty-three, the group of lists used may be the group of lists shown in FIG. 6. The map processor 602 uses the priority information included with each segment to selected one of the priority table lists. For example, if the priority associated with a segment is priority 1, then the map processor uses priority table list 1, shown at 624, to map the segment data.
  • The map processor [0046] 602 uses the sequence identifier included with each segment to indirectly map a block in the selected priority table list to a block in the memory 404 where the segment will be stored. For example, the map processor uses the upper four bits of the sequence identifier to select one of sixteen entries in the selected priority table list. The contents of the entry in the selected priority table list will be used as the block address 614.
  • However, if the entry in the selected priority list contains an invalid block address, then the map processor operates to obtain an available block memory address from the free block list [0047] 620. The map processor enters this newly obtained block address into the entry in the selected priority table list, and validates the valid bit. Thereafter, sequence numbers whose upper bits point to this entry in the selected priority table list will obtain this block address to be used to store the segment data. The valid lists contain bits that indicate whether an address in the corresponding priority table lists is valid. These bits are validated or invalidated depending if the specific block of memory is being used or if all of the segments in that block have been sent.
  • An example of the mapping process will now be described. Assume the memory [0048] 404 is configured to have a total of four Megabytes of storage. This allocation will support segments transmitted from sixty-four source processors; each allocated 64 k bytes to store all of their incoming segments. These 64 k bytes will be further subdivided into 16 blocks representing a total of 1024 segment storage locations. Each segment storage location contains a block of 64 bytes of data. The incoming segment will be stripped of its segment header and CRC, and the remaining 64-byte segment payload will fit within the 64-byte block.
  • The 16 blocks (or groups) representing a total of 1024 segment storage locations can be dynamically allocated to any of the segment priorities as needed. The four MSB's of the sequence number included with each segment indirectly maps into one of these 16 blocks of memory. The mapping is stored in the priority lists and any unused groups are stored in the free list FIFO [0049] 620.
  • The free list FIFO [0050] 620 hold 16 group addresses. Each group address is 4-bits wide and directly maps to a memory address as the block address 614. There are a total of 64 free list FIFOs, one for each transmitting source.
  • There are 5 priority table lists and each can store up to 16 block addresses. The valid bit associated with each entry will determine if a valid block address is stored in that entry. After initialization or reset, the free list FIFO [0051] 620 will contain all 16 block addresses and all of the valid bits associated with the priority table lists will be cleared to indicate that no entries in the lists are valid.
  • When a segment arrives, the four most significant bits (MSB) of the sequence number [0052] 604 are used to find the block address 614 that the segment should be written to in the memory 404. The source 608 and priority 606 of the segment will determine which priority table list to use, and the four MSB's of the sequence number 604 will be used to address into that table to find a selected entry.
  • First, the valid bit for the selected entry will be checked to determine if a group has already been assigned to the sequence number. If a group has been assigned, the valid bit will be a one, and the contents of that entry will be used as the block address [0053] 614 for addressing the memory 404. If the valid bit is not set, then a new group will be obtained from the free list FIFO 620, inserted into the table list at the selected entry, and the corresponding valid bit will be set to a one. Thus, segments that follow having the same source, priority, and four MSB sequence number will use this new group address.
  • In this example, it will be assumed that a segment is received from a source processor having a source identifier [0054] 608 of twenty-three with a priority of zero, and the four MSB's of the sequence number are 0011. A check in the priority 0 table list 622 at entry three shows that the valid bit is zero, as indicated at 644. A new address group is needed and the map processor operates to obtain it from the free list FIFO 620. The new address group has the value 0111 and is inserted into the table list 622 at entry three and will also be used as block address 614 to access the memory 404. The valid bit at entry three will then be set to a one to indicate that the address is valid (not shown in the FIG. 6).
  • The lower 6 bits of the sequence number [0055] 604 are directly mapped into one of the 64 memory blocks as the sequence address 612. If another segment comes in from transmitting source twenty-three with a sequence number of (0100xxxxxx binary) and a priority of two, the map processor 602 will map a value of 1111 to the block address 614. This value is determined from the priority 2 table list as shown at 626. Also shown is the control channel 422 that allows information from the map processor to flow to the Dequeue logic during the dequeue process.
  • FIG. 7 shows one embodiment of the pointers [0056] 418 for use in a reordering system in accordance with the present invention. The pointers 418 include a map list 702 and a map pointer 704 for each priority level transmitted by each source processor. Therefore, since there are five priority levels in the present example, there are five map lists 702(1-5) and five map pointers 704(1-5) per transmitting source processor. In a system where there are sixty-four transmitting source processors and five priority levels, the total number of map list 702 and associated map pointer 704 sets will be 320.
  • The map list [0057] 702 includes a current frame segment (CFS) pointer 706 and a first invalid segment (FIS) pointer 708. The CFS pointer is the location of a segment that contains the start (head) of a frame currently being stored in the memory 404. The FIS pointer 708 is the first location, relative to the CFS, indicating where a segment has not yet arrived. In other words, it is the next missing segment in a series of segments starting from the CFS pointer. Values for both the CFS and FIS pointers are entered into the map pointer 704.
  • The map pointer [0058] 704 also includes a length value 710 and an offset value 712. The length value is the total length of the single frame (in bytes), whose head is located at the CFS pointer. The length value can be found at the head of a segment or it may be embedded within a segment if the frame ends within the segment and the next frame is packed at the tail of the ending frame. The offset value, measured in bytes, determines where the frame head starts within a segment. Again, the offset value can be found at the head of a segment, for example, by receiving a segment with an offset of zero or extracted from a segment while de-queuing.
  • The map list [0059] 702 keeps track of all the segments that have arrived and are ready to be reordered. For one source/priority, the corresponding map list contains 1024 bits of data. These bits directly map to the 1024 segment storage locations in the memory 404. The sequence number is used to directly map the bits in the map list to the segments that are stored in memory. As a result, a bit in the map list will be set valid when a segment arrives, and cleared when the segment is de-queued.
  • FIG. 8 shows a flow diagram [0060] 800 for reordering segments in accordance with the present invention. At block 802, data frames are received at one or more source processors for transmission to a destination processor via one or more network fabrics.
  • At block [0061] 804, the frames are segmented and are encoded with a sequence identifier, a priority value and a source identifier. In one embodiment, the segment data payload is 64-bytes long. At block 806, the segments are transmitted to a destination processor via one or more network fabrics.
  • At block [0062] 808, the transmitted segments are received at a destination processor. The destination processor receives segments from one or more transmitting source processors via the network fabrics.
  • At block [0063] 810, the source identifier, priority level, and sequence identifier are extracted from each received segment. For example, the segment decoder 603 extracts this information from each received segment. At block 812, the extracted information is used to determine a memory address in a memory where each segment is stored. For example, as shown in FIG. 6, the map processor 602 operates to use the extracted information received from the decoder 603 to index into the map 414 to determine at least a portion of the memory address where a received segment will be stored.
  • At block [0064] 814, each received segment is stored into memory at the address determined from the previous step. At block 816, the pointers 418 are updated to reflect how many segments have been received.
  • The above steps describe the flow of segment data from transmitting source processors to a destination processor via one or more network fabrics. Once the segments are received at the destination processor, they are stored into a memory in accordance with the above steps. The following steps are used to unload the segments from the memory for transmission to another network entity. In the process of unloading the segments, the segments and corresponding data frames are reordered in accordance with the invention. It should be noted that the reception, reordering, and transmission of frames as described by the reordering process of FIG. 8 is a continuous process. Therefore, frames may continue to be received during the reorder and transmission processes. [0065]
  • At block [0066] 818, a frame check is performed to determine if enough segments have been received and stored into the memory to form a complete frame. For example, as segments are received and stored in the memory, and map lists are used to keep track of the sequential number of segments that have been received. For example, if the memory map as provided in FIG. 7 is used, the CFS pointer, the FIS pointer, the table entries, the length, and the offset values are used to calculate if a frame is contained within the two pointers. If it is determined that a complete frame has been received and is stored in the memory, a ready flag that is associated with the context that was just checked is activated to indicate that a frame can be dequeued.
  • At block [0067] 820, assuming a complete frame has been received the completed frame is unloaded from the memory. The logic reads the CFS and FIS pointers and length from the associated context that was selected and dequeues the associated frame.
  • At block [0068] 822, a test is performed after the current frame is unloaded to determine if there are enough segments in memory to unload another frame. For example, there may be another frame beginning with the next segment directly after the current frame that was unloaded. In another situation, there may be another frame that is partially packed within the last segment of the current frame. For example, the header for the next frame is packed into the last segment of the current frame. If there are no other complete frames to unload, the method proceeds to block 824. If there is another frame to unload, the method proceeds back to block 820.
  • When the frames are being unloaded, the CFS pointer will be updated to the point where the last frame ended to become the new CFS pointer. If another frame is found, the length of that next frame, the FIS pointer, and the new CFS pointer are used to determine if next frame can be dequeued. This process will continue until there are no more frames that can be dequeued. [0069]
  • At block [0070] 824, when there are no more frames to be dequeued, the Dequeue logic writes back the new CFS pointer, length and offset to the Context Memory. The new CFS pointer will be pointing to indicate the location of the start of the next frame in memory.
  • At block [0071] 826 the memory usage maps are updated. For example, the last function that is performed is that all of the valid bits from the old CFS pointer to the new CFS pointer are cleared, and if any memory blocks need to be de-allocated, they are put back onto the free list FIFO 620 so that they may be reused to store additional received segments. The method then continues at block 818.
  • In accordance with the present invention, segments transmitted from a particular source are reordered to have the same order as when initially transmitted. Therefore, one or more embodiments included in the present invention provide a system for reordering segments in a switching network. After the context is dequeued, and there are no more frames that can be dequeued from that context, the Dequeue logic clears the selected ready flag. The segments associated with the frame are read out of the memory. The frames are then passed to the segment transmitter [0072] 410 and the frames/segments are sent on to the next destination in the system.
  • Thus, the present invention includes a system for reordering packet segments in a packet switch network. The embodiments described above are illustrative of the present invention and are not intended to limit the scope of the invention to the particular embodiments described. Accordingly, while several embodiments of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit or essential characteristics thereof. Accordingly, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims. [0073]

Claims (16)

What is claimed is:
1. A system for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics, the system comprising:
encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted;
a memory located at the destination processor;
map logic at the destination processor that operates to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region; and
a Dequeue processor coupled to the memory and operable to determine when enough packet segments are stored in the memory to form a complete data frame, wherein the Dequeue processor operates to output the packet segments that form the complete data frame.
2. The system of claim 1, wherein the memory regions are associated with the source processors, one memory region per source processor.
3. The system of claim 1, wherein the map logic includes a map processor and map tables.
4. The system of claim 1, wherein the segment identifier includes a source identifier and a segment identifier.
5. The system of claim 4, wherein the segment identifier includes priority level indicator that is chosen from selected priority levels.
6. The system of claim 5, wherein the one or more memory regions are associated with the source processors and the selected priority levels, and wherein the total number of memory regions is equal to the number of source processors times the number of selected priority levels.
7. A method for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics, the method comprising steps of:
including a segment identifier with each of the packet segments before they are transmitted from the source processors;
defining one or more memory regions in a memory located at the destination processor;
mapping the segment identifier associated with each received packet segment to a selected memory region, wherein the received packet segment is stored at the selected memory region;
updating a memory map;
identifying when enough packet segments have been received to form a complete data frame; and
outputting the complete data frame.
8. The method of claim 7, wherein the step of including further comprises a step of including a priority level indicator with each of the packet segments before they are transmitted from the source processors, wherein the priority level indicator is chosen from selected priority levels.
9. The method of claim 8, wherein the step of defining further comprises a step of defining the one or more memory regions so that the total number of memory regions is equal to the number of source processors times the number of selected priority levels.
10. The method of claim 7, further comprising a step of including a new segment identifier with each of the packet segments before they are outputted by the destination processor.
11. A destination processor for reordering packet segments in a packet switch network, wherein one or more source processors transmit the packet segments to the destination processor via one or more network fabrics, and wherein the packets are encoded with a unique segment identifier before transmission from the source processors, the destination processor comprising:
a memory;
map logic that operates to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region; and
a Dequeue processor coupled to the memory and operable to determine when enough packet segments are stored in the memory to form a complete data frame, wherein the Dequeue processor operates to output the complete data frame.
12. The system of claim 11, wherein the memory regions are associated with the source processors, one memory region per source processor.
13. The system of claim 11, wherein the map logic includes a map processor and map tables.
14. The system of claim 11, wherein the segment identifier includes a source identifier and a segment identifier.
15. The system of claim 14, wherein the segment identifier includes priority level indicator that is chosen from selected priority levels.
16. The system of claim 15, wherein the one or more memory regions are associated with the source processors and the selected priority levels, and wherein the total number of memory regions is equal to the number of source processors times the number of selected priority levels.
US10/295,399 2002-11-14 2002-11-14 System for reordering sequenced based packet segments in a switching network Abandoned US20040098509A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/295,399 US20040098509A1 (en) 2002-11-14 2002-11-14 System for reordering sequenced based packet segments in a switching network

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/295,399 US20040098509A1 (en) 2002-11-14 2002-11-14 System for reordering sequenced based packet segments in a switching network
US11/759,194 US7590721B2 (en) 2002-11-14 2007-06-06 Reordering sequence based channels

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/759,194 Continuation US7590721B2 (en) 2002-11-14 2007-06-06 Reordering sequence based channels

Publications (1)

Publication Number Publication Date
US20040098509A1 true US20040098509A1 (en) 2004-05-20

Family

ID=32297187

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/295,399 Abandoned US20040098509A1 (en) 2002-11-14 2002-11-14 System for reordering sequenced based packet segments in a switching network
US11/759,194 Active 2023-05-20 US7590721B2 (en) 2002-11-14 2007-06-06 Reordering sequence based channels

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/759,194 Active 2023-05-20 US7590721B2 (en) 2002-11-14 2007-06-06 Reordering sequence based channels

Country Status (1)

Country Link
US (2) US20040098509A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080313684A1 (en) * 2007-06-13 2008-12-18 Glenn Darrell Batalden Determining a Transmission Order for Frames Based on Bit Reversals of Sequence Numbers
US20120011271A1 (en) * 2010-07-07 2012-01-12 Futurewei Technologies, Inc. System and Method for Content and Application Acceleration in a Wireless Communications System

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8281155B1 (en) * 2000-11-02 2012-10-02 Intel Corporation Content protection using block reordering
US20060268855A1 (en) * 2005-05-31 2006-11-30 Caterpillar Inc. Communication apparatus for real-time embedded control
KR20090099734A (en) * 2008-03-18 2009-09-23 삼성전자주식회사 Interface system based on stream and method for controlling the same
JP5104717B2 (en) * 2008-10-23 2012-12-19 富士通株式会社 Data distribution apparatus, relay apparatus, data distribution method, and data distribution program
JP5903873B2 (en) * 2011-12-19 2016-04-13 富士通株式会社 Storage device, storage device control method, and storage device control program
KR102014118B1 (en) 2012-10-19 2019-08-26 삼성전자주식회사 Method and Apparatus for Channel Management of Sub-Channel Scheme in Network Backbone System based Advanced Extensible Interface
US9054998B2 (en) * 2013-02-06 2015-06-09 Freescale Semiconductor, Inc. System and method for maintaining packet order in an ordered data stream

Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330824A (en) * 1978-08-17 1982-05-18 Compagnie Internationale Pour L'informatique Cii Honeywell Bull (Societe Anonyme) Universal arrangement for the exchange of data between the memories and the processing devices of a computer
US4394725A (en) * 1973-11-30 1983-07-19 Compagnie Honeywell Bull Apparatus and method for transferring information units between processes in a multiprocessing system
US4574451A (en) * 1982-12-22 1986-03-11 General Electric Company Method for producing an article with a fluid passage
US4740954A (en) * 1986-12-31 1988-04-26 Bell Communications Research, Inc. Multicast routing algorithm
US5550823A (en) * 1994-04-28 1996-08-27 Nec Corporation Method and apparatus for performing priority control for cells in output buffer type ATM switch
US5555543A (en) * 1995-01-03 1996-09-10 International Business Machines Corporation Crossbar switch apparatus and protocol
US5606370A (en) * 1994-07-11 1997-02-25 Samsung Electronics Co., Ltd. Sync restoring method for variable-length decoding and apparatus thereof
US5845145A (en) * 1995-12-21 1998-12-01 Apple Computer, Inc. System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order
US5860085A (en) * 1994-08-01 1999-01-12 Cypress Semiconductor Corporation Instruction set for a content addressable memory array with read/write circuits and an interface register logic block
US5898689A (en) * 1992-12-04 1999-04-27 Lucent Technologies Inc. Packet network interface
US5905911A (en) * 1990-06-29 1999-05-18 Fujitsu Limited Data transfer system which determines a size of data being transferred between a memory and an input/output device
US5909440A (en) * 1996-12-16 1999-06-01 Juniper Networks High speed variable length best match look-up in a switching device
US5923893A (en) * 1997-09-05 1999-07-13 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US5982749A (en) * 1996-03-07 1999-11-09 Lsi Logic Corporation ATM communication system interconnect/termination unit
US6026092A (en) * 1996-12-31 2000-02-15 Northern Telecom Limited High performance fault tolerant switching system for multimedia satellite and terrestrial communications networks
US6067408A (en) * 1993-05-27 2000-05-23 Advanced Micro Devices, Inc. Full duplex buffer management and apparatus
US6172927B1 (en) * 1997-04-01 2001-01-09 Ramtron International Corporation First-in, first-out integrated circuit memory device incorporating a retransmit function
US6192465B1 (en) * 1998-09-21 2001-02-20 Advanced Micro Devices, Inc. Using multiple decoders and a reorder queue to decode instructions out of order
US6246684B1 (en) * 1997-12-24 2001-06-12 Nortel Networks Limited Method and apparatus for re-ordering data packets in a network environment
US20010037435A1 (en) * 2000-05-31 2001-11-01 Van Doren Stephen R. Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system
US20020054602A1 (en) * 2000-11-08 2002-05-09 Masami Takahashi Shared buffer type variable length packet switch
US6389489B1 (en) * 1999-03-17 2002-05-14 Motorola, Inc. Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size
US20020061022A1 (en) * 1999-08-27 2002-05-23 Allen James Johnson Network switch using network processor and methods
US20020099855A1 (en) * 1999-08-27 2002-07-25 Brian Mitchell Bass Network processor, memory organization and methods
US6434115B1 (en) * 1998-07-02 2002-08-13 Pluris, Inc. System and method for switching packets in a network
US6442674B1 (en) * 1998-12-30 2002-08-27 Intel Corporation Method and system for bypassing a fill buffer located along a first instruction path
US20020122386A1 (en) * 2001-03-05 2002-09-05 International Business Machines Corporation High speed network processor
US20020165947A1 (en) * 2000-09-25 2002-11-07 Crossbeam Systems, Inc. Network application apparatus
US6493347B2 (en) * 1996-12-16 2002-12-10 Juniper Networks, Inc. Memory organization in a switching device
US20030035427A1 (en) * 2001-08-14 2003-02-20 Mehdi Alasti Method and apparatus for arbitration scheduling with a penalty for a switch fabric
US6570876B1 (en) * 1998-04-01 2003-05-27 Hitachi, Ltd. Packet switch and switching method for switching variable length packets
US6574194B1 (en) * 1998-12-18 2003-06-03 Cypress Semiconductor Corporation Architecture of data communications switching system and associated method
US6687768B2 (en) * 2000-07-05 2004-02-03 Sony Corporation Data stream generation apparatus and method of same, variable length coded data stream generation apparatus and method of same, and camera system
US6735647B2 (en) * 2002-09-05 2004-05-11 International Business Machines Corporation Data reordering mechanism for high performance networks
US6754741B2 (en) * 2001-05-10 2004-06-22 Pmc-Sierra, Inc. Flexible FIFO system for interfacing between datapaths of variable length
US6795870B1 (en) * 2000-04-13 2004-09-21 International Business Machines Corporation Method and system for network processor scheduler
US20040230735A1 (en) * 2003-05-15 2004-11-18 Moll Laurent R. Peripheral bus switch having virtual peripheral bus and configurable host bridge
US6907041B1 (en) * 2000-03-07 2005-06-14 Cisco Technology, Inc. Communications interconnection network with distributed resequencing
US6967951B2 (en) * 2002-01-11 2005-11-22 Internet Machines Corp. System for reordering sequenced based packets in a switching network

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754451A (en) 1986-08-06 1988-06-28 American Telephone And Telegraph Company, At&T Bell Laboratories N-by-N "knockout" switch for a high-performance packet switching system with variable length packets
US7349393B2 (en) * 1999-12-02 2008-03-25 Verizon Business Global Llc Method and system for implementing an improved universal packet switching capability in a data switch
US6629147B1 (en) * 2000-03-31 2003-09-30 Intel Corporation Segmentation and reassembly of data frames
US6781992B1 (en) * 2000-11-30 2004-08-24 Netrake Corporation Queue engine for reassembling and reordering data packets in a network
US6934760B1 (en) * 2001-02-04 2005-08-23 Cisco Technology, Inc. Method and apparatus for resequencing of packets into an original ordering using multiple resequencing components
US7403525B2 (en) * 2002-05-15 2008-07-22 Broadcom Corporation Efficient routing of packet data in a scalable processing resource
US7480308B1 (en) * 2004-03-29 2009-01-20 Cisco Technology, Inc. Distributing packets and packets fragments possibly received out of sequence into an expandable set of queues of particular use in packet resequencing and reassembly
US7529245B1 (en) * 2005-04-04 2009-05-05 Sun Microsystems, Inc. Reorder mechanism for use in a relaxed order input/output system

Patent Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394725A (en) * 1973-11-30 1983-07-19 Compagnie Honeywell Bull Apparatus and method for transferring information units between processes in a multiprocessing system
US4330824A (en) * 1978-08-17 1982-05-18 Compagnie Internationale Pour L'informatique Cii Honeywell Bull (Societe Anonyme) Universal arrangement for the exchange of data between the memories and the processing devices of a computer
US4574451A (en) * 1982-12-22 1986-03-11 General Electric Company Method for producing an article with a fluid passage
US4740954A (en) * 1986-12-31 1988-04-26 Bell Communications Research, Inc. Multicast routing algorithm
US5905911A (en) * 1990-06-29 1999-05-18 Fujitsu Limited Data transfer system which determines a size of data being transferred between a memory and an input/output device
US5898689A (en) * 1992-12-04 1999-04-27 Lucent Technologies Inc. Packet network interface
US6067408A (en) * 1993-05-27 2000-05-23 Advanced Micro Devices, Inc. Full duplex buffer management and apparatus
US5550823A (en) * 1994-04-28 1996-08-27 Nec Corporation Method and apparatus for performing priority control for cells in output buffer type ATM switch
US5606370A (en) * 1994-07-11 1997-02-25 Samsung Electronics Co., Ltd. Sync restoring method for variable-length decoding and apparatus thereof
US5860085A (en) * 1994-08-01 1999-01-12 Cypress Semiconductor Corporation Instruction set for a content addressable memory array with read/write circuits and an interface register logic block
US5555543A (en) * 1995-01-03 1996-09-10 International Business Machines Corporation Crossbar switch apparatus and protocol
US5845145A (en) * 1995-12-21 1998-12-01 Apple Computer, Inc. System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order
US5982749A (en) * 1996-03-07 1999-11-09 Lsi Logic Corporation ATM communication system interconnect/termination unit
US5909440A (en) * 1996-12-16 1999-06-01 Juniper Networks High speed variable length best match look-up in a switching device
US6493347B2 (en) * 1996-12-16 2002-12-10 Juniper Networks, Inc. Memory organization in a switching device
US6026092A (en) * 1996-12-31 2000-02-15 Northern Telecom Limited High performance fault tolerant switching system for multimedia satellite and terrestrial communications networks
US6172927B1 (en) * 1997-04-01 2001-01-09 Ramtron International Corporation First-in, first-out integrated circuit memory device incorporating a retransmit function
US5923893A (en) * 1997-09-05 1999-07-13 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US6246684B1 (en) * 1997-12-24 2001-06-12 Nortel Networks Limited Method and apparatus for re-ordering data packets in a network environment
US6570876B1 (en) * 1998-04-01 2003-05-27 Hitachi, Ltd. Packet switch and switching method for switching variable length packets
US6434115B1 (en) * 1998-07-02 2002-08-13 Pluris, Inc. System and method for switching packets in a network
US6192465B1 (en) * 1998-09-21 2001-02-20 Advanced Micro Devices, Inc. Using multiple decoders and a reorder queue to decode instructions out of order
US6574194B1 (en) * 1998-12-18 2003-06-03 Cypress Semiconductor Corporation Architecture of data communications switching system and associated method
US6442674B1 (en) * 1998-12-30 2002-08-27 Intel Corporation Method and system for bypassing a fill buffer located along a first instruction path
US6389489B1 (en) * 1999-03-17 2002-05-14 Motorola, Inc. Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size
US20020099855A1 (en) * 1999-08-27 2002-07-25 Brian Mitchell Bass Network processor, memory organization and methods
US20020061022A1 (en) * 1999-08-27 2002-05-23 Allen James Johnson Network switch using network processor and methods
US6907041B1 (en) * 2000-03-07 2005-06-14 Cisco Technology, Inc. Communications interconnection network with distributed resequencing
US6795870B1 (en) * 2000-04-13 2004-09-21 International Business Machines Corporation Method and system for network processor scheduler
US20010037435A1 (en) * 2000-05-31 2001-11-01 Van Doren Stephen R. Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system
US6687768B2 (en) * 2000-07-05 2004-02-03 Sony Corporation Data stream generation apparatus and method of same, variable length coded data stream generation apparatus and method of same, and camera system
US20020165947A1 (en) * 2000-09-25 2002-11-07 Crossbeam Systems, Inc. Network application apparatus
US20020054602A1 (en) * 2000-11-08 2002-05-09 Masami Takahashi Shared buffer type variable length packet switch
US20020122386A1 (en) * 2001-03-05 2002-09-05 International Business Machines Corporation High speed network processor
US6754741B2 (en) * 2001-05-10 2004-06-22 Pmc-Sierra, Inc. Flexible FIFO system for interfacing between datapaths of variable length
US20030035427A1 (en) * 2001-08-14 2003-02-20 Mehdi Alasti Method and apparatus for arbitration scheduling with a penalty for a switch fabric
US6967951B2 (en) * 2002-01-11 2005-11-22 Internet Machines Corp. System for reordering sequenced based packets in a switching network
US6735647B2 (en) * 2002-09-05 2004-05-11 International Business Machines Corporation Data reordering mechanism for high performance networks
US20040230735A1 (en) * 2003-05-15 2004-11-18 Moll Laurent R. Peripheral bus switch having virtual peripheral bus and configurable host bridge

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080313684A1 (en) * 2007-06-13 2008-12-18 Glenn Darrell Batalden Determining a Transmission Order for Frames Based on Bit Reversals of Sequence Numbers
US7986705B2 (en) * 2007-06-13 2011-07-26 International Business Machines Corporation Determining a transmission order for frames based on bit reversals of sequence numbers
US20120011271A1 (en) * 2010-07-07 2012-01-12 Futurewei Technologies, Inc. System and Method for Content and Application Acceleration in a Wireless Communications System
US9420441B2 (en) * 2010-07-07 2016-08-16 Futurewei Technologies, Inc. System and method for content and application acceleration in a wireless communications system

Also Published As

Publication number Publication date
US20070237151A1 (en) 2007-10-11
US7590721B2 (en) 2009-09-15

Similar Documents

Publication Publication Date Title
US5905725A (en) High speed switching device
US5689512A (en) ATM cell interface and method for dispatching an ATM cell
EP0797335B1 (en) Network adapter
US5982771A (en) Controlling bandwidth allocation using a pace counter
DE69737357T2 (en) Storage organization in a communication device
US5289470A (en) Flexible scheme for buffer space allocation in networking devices
US7319669B1 (en) Method and system for controlling packet flow in networks
JP2990345B2 (en) Network Interface
US5398245A (en) Packet processing method and apparatus
US7450583B2 (en) Device to receive, buffer, and transmit packets of data in a packet switching network
US6088777A (en) Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages
EP1157518B1 (en) Method and apparatus for data re-assembly with a high performance network interface
US5396490A (en) Packet reassembly method and apparatus
US7596142B1 (en) Packet processing in a packet switch with improved output data distribution
CA2112528C (en) Packet switching system for forwarding packets from input buffers using idle/busy status of output buffers
AU677125B2 (en) Connectionless communication system
JP3050399B2 (en) Broadcast packet-switched network
EP1275224B1 (en) Filtering and route lookup in a switching device
US6151318A (en) Method and apparatus for encapsulating ATM cells in a broadband network
US5726985A (en) ATM communication system interconnect/termination unit
JP3443264B2 (en) Multicast routing is improved in multistage networks
US6320859B1 (en) Early availability of forwarding control information
US5689505A (en) Buffering of multicast cells in switching networks
US7263103B2 (en) Receive queue descriptor pool
US6956853B1 (en) Receive processing with network protocol bypass

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNET MACHINES CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ALFANO, VIC;REEL/FRAME:013498/0804

Effective date: 20021105

AS Assignment

Owner name: TOPSIDE RESEARCH, LLC, VIRGINIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNET MACHINES CORP.;REEL/FRAME:019211/0567

Effective date: 20070418

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION