ATE325417T1 - Vorrichtung und verfahren zum kodieren einer selbstvorladefunktion - Google Patents

Vorrichtung und verfahren zum kodieren einer selbstvorladefunktion

Info

Publication number
ATE325417T1
ATE325417T1 AT03705709T AT03705709T ATE325417T1 AT E325417 T1 ATE325417 T1 AT E325417T1 AT 03705709 T AT03705709 T AT 03705709T AT 03705709 T AT03705709 T AT 03705709T AT E325417 T1 ATE325417 T1 AT E325417T1
Authority
AT
Austria
Prior art keywords
coding
self
precharging function
precharging
function
Prior art date
Application number
AT03705709T
Other languages
English (en)
Inventor
Narendra Khandekar
Michael Williams
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE325417T1 publication Critical patent/ATE325417T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Communication Control (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
AT03705709T 2002-01-28 2003-01-09 Vorrichtung und verfahren zum kodieren einer selbstvorladefunktion ATE325417T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/058,567 US6829184B2 (en) 2002-01-28 2002-01-28 Apparatus and method for encoding auto-precharge

Publications (1)

Publication Number Publication Date
ATE325417T1 true ATE325417T1 (de) 2006-06-15

Family

ID=27609618

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03705709T ATE325417T1 (de) 2002-01-28 2003-01-09 Vorrichtung und verfahren zum kodieren einer selbstvorladefunktion

Country Status (8)

Country Link
US (1) US6829184B2 (de)
EP (1) EP1470553B1 (de)
KR (1) KR100619202B1 (de)
CN (1) CN1751358B (de)
AT (1) ATE325417T1 (de)
DE (1) DE60304999T2 (de)
TW (1) TWI304932B (de)
WO (1) WO2003065376A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10354034B4 (de) * 2003-11-19 2005-12-08 Infineon Technologies Ag Verfahren zum Betreiben einer Halbleiterspeichervorrichtung und Halbleiterspeichervorrichtung
US20060095652A1 (en) * 2004-10-29 2006-05-04 Hermann Ruckerbauer Memory device and method for receiving instruction data
US7761656B2 (en) * 2007-08-22 2010-07-20 Advanced Micro Devices, Inc. Detection of speculative precharge
US8521951B2 (en) * 2008-01-16 2013-08-27 S. Aqua Semiconductor Llc Content addressable memory augmented memory
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
KR20130046122A (ko) * 2011-10-27 2013-05-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
US9390785B2 (en) 2014-03-27 2016-07-12 Intel Corporation Method, apparatus and system for determining a write recovery time of a memory based on temperature
KR20170068719A (ko) * 2015-12-09 2017-06-20 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
US5511024A (en) 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system
JP3432548B2 (ja) * 1993-07-26 2003-08-04 株式会社日立製作所 半導体記憶装置
JP4084428B2 (ja) * 1996-02-02 2008-04-30 富士通株式会社 半導体記憶装置
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6243768B1 (en) * 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
JP4390304B2 (ja) * 1998-05-26 2009-12-24 株式会社ルネサステクノロジ 半導体集積回路装置
JP2000163965A (ja) * 1998-11-27 2000-06-16 Mitsubishi Electric Corp 同期型半導体記憶装置
US6330636B1 (en) 1999-01-29 2001-12-11 Enhanced Memory Systems, Inc. Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
JP2001118383A (ja) * 1999-10-20 2001-04-27 Fujitsu Ltd リフレッシュを自動で行うダイナミックメモリ回路
US6151236A (en) * 2000-02-29 2000-11-21 Enhanced Memory Systems, Inc. Enhanced bus turnaround integrated circuit dynamic random access memory device
KR100424118B1 (ko) * 2001-05-03 2004-03-24 주식회사 하이닉스반도체 클럭 신호의 주파수 정보를 이용하여 셀 동작을 제어하는동기식 반도체 메모리 장치

Also Published As

Publication number Publication date
DE60304999D1 (de) 2006-06-08
US6829184B2 (en) 2004-12-07
US20030142557A1 (en) 2003-07-31
DE60304999T2 (de) 2007-01-25
CN1751358B (zh) 2010-11-17
CN1751358A (zh) 2006-03-22
TW200302418A (en) 2003-08-01
WO2003065376A1 (en) 2003-08-07
KR20040081152A (ko) 2004-09-20
KR100619202B1 (ko) 2006-09-08
EP1470553B1 (de) 2006-05-03
EP1470553A1 (de) 2004-10-27
TWI304932B (en) 2009-01-01

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