ATE309575T1 - Speicherbusschnittstelle mit geringem energieverbrauch - Google Patents

Speicherbusschnittstelle mit geringem energieverbrauch

Info

Publication number
ATE309575T1
ATE309575T1 AT02796125T AT02796125T ATE309575T1 AT E309575 T1 ATE309575 T1 AT E309575T1 AT 02796125 T AT02796125 T AT 02796125T AT 02796125 T AT02796125 T AT 02796125T AT E309575 T1 ATE309575 T1 AT E309575T1
Authority
AT
Austria
Prior art keywords
bus interface
energy consumption
low energy
storage bus
memory bus
Prior art date
Application number
AT02796125T
Other languages
English (en)
Inventor
Jeffrey Wilcox
Noam Yosef
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE309575T1 publication Critical patent/ATE309575T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3253Power saving in bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
  • Small-Scale Networks (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT02796125T 2002-01-02 2002-12-31 Speicherbusschnittstelle mit geringem energieverbrauch ATE309575T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/038,960 US7000065B2 (en) 2002-01-02 2002-01-02 Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
PCT/US2002/041742 WO2003058467A1 (en) 2002-01-02 2002-12-31 Power reduction in a memory bus interface

Publications (1)

Publication Number Publication Date
ATE309575T1 true ATE309575T1 (de) 2005-11-15

Family

ID=21902905

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02796125T ATE309575T1 (de) 2002-01-02 2002-12-31 Speicherbusschnittstelle mit geringem energieverbrauch

Country Status (9)

Country Link
US (3) US7000065B2 (de)
EP (1) EP1463998B1 (de)
KR (1) KR100611266B1 (de)
CN (1) CN1613065B (de)
AT (1) ATE309575T1 (de)
AU (1) AU2002360836A1 (de)
DE (1) DE60207303T2 (de)
TW (1) TWI279680B (de)
WO (1) WO2003058467A1 (de)

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US7800621B2 (en) * 2005-05-16 2010-09-21 Ati Technologies Inc. Apparatus and methods for control of a memory controller
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US7945793B2 (en) * 2006-08-11 2011-05-17 Intel Corporation Interface frequency modulation to allow non-terminated operation and power reduction
US7730337B2 (en) * 2007-01-24 2010-06-01 Via Technologies, Inc. Method and apparatus for asserting a hardware pin to disable a data bus connecting a processor and a chipset during power saving state
US7605628B2 (en) * 2007-05-07 2009-10-20 Lsi Corporation System for glitch-free delay updates of a standard cell-based programmable delay
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US9465756B2 (en) * 2009-12-23 2016-10-11 Violin Memory Inc. Configurable interconnection system
US8799685B2 (en) 2010-08-25 2014-08-05 Advanced Micro Devices, Inc. Circuits and methods for providing adjustable power consumption
US8356155B2 (en) * 2010-09-13 2013-01-15 Advanced Micro Devices, Inc. Dynamic RAM Phy interface with configurable power states
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
US9285824B2 (en) * 2012-05-01 2016-03-15 Marvell World Trade Ltd. Systems and methods for DQS gating
US9658642B2 (en) * 2013-07-01 2017-05-23 Intel Corporation Timing control for unmatched signal receiver
US10127100B2 (en) 2016-06-03 2018-11-13 International Business Machines Corporation Correcting a data storage error caused by a broken conductor using bit inversion
CN111240596A (zh) * 2020-01-14 2020-06-05 深圳市德名利电子有限公司 一种判断闪存的操作接口模式的方法和装置以及设备

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US7216240B2 (en) * 2002-12-11 2007-05-08 Intel Corporation Apparatus and method for address bus power control
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Also Published As

Publication number Publication date
US20030126485A1 (en) 2003-07-03
US20060190751A1 (en) 2006-08-24
WO2003058467A1 (en) 2003-07-17
EP1463998B1 (de) 2005-11-09
TW200301859A (en) 2003-07-16
KR100611266B1 (ko) 2006-08-10
US7000065B2 (en) 2006-02-14
US20130103867A1 (en) 2013-04-25
US10102157B2 (en) 2018-10-16
DE60207303T2 (de) 2006-03-30
DE60207303D1 (de) 2005-12-15
EP1463998A1 (de) 2004-10-06
AU2002360836A1 (en) 2003-07-24
CN1613065B (zh) 2010-05-26
CN1613065A (zh) 2005-05-04
KR20040070301A (ko) 2004-08-06
US8176240B2 (en) 2012-05-08
TWI279680B (en) 2007-04-21

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