ATE236427T1 - Verfahren zur erzeugung von isa simulatoren und assemblierern aus einer maschinenbeschreibung - Google Patents

Verfahren zur erzeugung von isa simulatoren und assemblierern aus einer maschinenbeschreibung

Info

Publication number
ATE236427T1
ATE236427T1 AT98956368T AT98956368T ATE236427T1 AT E236427 T1 ATE236427 T1 AT E236427T1 AT 98956368 T AT98956368 T AT 98956368T AT 98956368 T AT98956368 T AT 98956368T AT E236427 T1 ATE236427 T1 AT E236427T1
Authority
AT
Austria
Prior art keywords
generating
assemblers
simulators
machine description
hardware
Prior art date
Application number
AT98956368T
Other languages
English (en)
Inventor
David Carroll Fritz
Original Assignee
Production Languages Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Production Languages Corp filed Critical Production Languages Corp
Application granted granted Critical
Publication of ATE236427T1 publication Critical patent/ATE236427T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/10—Requirements analysis; Specification techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)
AT98956368T 1997-10-31 1998-10-30 Verfahren zur erzeugung von isa simulatoren und assemblierern aus einer maschinenbeschreibung ATE236427T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/962,433 US5949993A (en) 1997-10-31 1997-10-31 Method for the generation of ISA simulators and assemblers from a machine description
PCT/US1998/023063 WO1999023555A1 (en) 1997-10-31 1998-10-30 Method for the generation of isa simulators and assemblers from a machine description

Publications (1)

Publication Number Publication Date
ATE236427T1 true ATE236427T1 (de) 2003-04-15

Family

ID=25505862

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98956368T ATE236427T1 (de) 1997-10-31 1998-10-30 Verfahren zur erzeugung von isa simulatoren und assemblierern aus einer maschinenbeschreibung

Country Status (10)

Country Link
US (1) US5949993A (de)
EP (1) EP1025492B1 (de)
JP (1) JP2001522084A (de)
KR (1) KR20010024576A (de)
AT (1) ATE236427T1 (de)
AU (1) AU1290699A (de)
CA (1) CA2307777A1 (de)
DE (1) DE69812990T2 (de)
IL (1) IL135810A0 (de)
WO (1) WO1999023555A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182242B1 (en) * 1998-04-22 2001-01-30 International Business Machines Corporation Generic device driver simulator and method
US6052524A (en) * 1998-05-14 2000-04-18 Software Development Systems, Inc. System and method for simulation of integrated hardware and software components
US6370492B1 (en) * 1998-12-08 2002-04-09 Lsi Logic Corporation Modified design representation for fast fault simulation of an integrated circuit
EP1202166B1 (de) * 2000-10-27 2003-08-06 Interactive Objects Software GmbH System zur Verifikation von Software-Anwendungsmodellen in Ketten von Software-Entwurfswerkzeugen
US7178138B2 (en) * 2001-01-24 2007-02-13 Texas Instruments Incorporated Method and tool for verification of algorithms ported from one instruction set architecture to another
ATE432499T1 (de) * 2001-06-29 2009-06-15 Texas Instruments Inc Verfahren zur verbesserung der sichtbarkeit von berechnung der effektiven adressen in pipelinearchitektur
US7475000B2 (en) * 2002-04-25 2009-01-06 Arc International, Plc Apparatus and method for managing integrated circuit designs
US20050049843A1 (en) * 2003-08-29 2005-03-03 Lee Hewitt Computerized extension apparatus and methods
US20060195732A1 (en) * 2005-02-11 2006-08-31 Joerg Deutschle Method and system for executing test cases for a device under verification
US7873947B1 (en) * 2005-03-17 2011-01-18 Arun Lakhotia Phylogeny generation
US7979771B2 (en) * 2006-04-04 2011-07-12 Permabit Technology Corporation Erasure coding technique for scalable and fault tolerant storage system
US8266571B2 (en) * 2008-06-10 2012-09-11 Oasis Tooling, Inc. Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow
KR101580258B1 (ko) * 2008-06-10 2015-12-28 오아시스 툴링 인코포레이티드 생산용 칩 디자인 워크플로우에서의 셀 무결성, 변경 및 기점에 대한 독립적인 평가 방법 및 장치
EP2718860A4 (de) 2011-06-10 2015-03-04 Oasis Tooling Inc Identifikation hierarchischer chipentwürfe als geistiges eigentum mithilfe von auszügen
US8966211B1 (en) * 2011-12-19 2015-02-24 Emc Corporation Techniques for dynamic binding of device identifiers to data storage devices
US9626170B2 (en) 2013-07-18 2017-04-18 Nxp Usa, Inc. Method and computer program product for disassembling a mixed machine code
US9134966B2 (en) 2013-12-12 2015-09-15 International Business Machines Corporation Management of mixed programming languages for a simulation environment
CN113515348B (zh) * 2021-07-16 2023-11-14 江苏师范大学 一种基于时机动作流的模拟器建模方法及装置

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686623A (en) * 1985-06-07 1987-08-11 International Business Machines Corporation Parser-based attribute analysis
AU7728187A (en) * 1986-09-12 1988-03-17 Digital Equipment Corporation Cad of logic circuits: rule structure for inserting new elements
US5644497A (en) * 1988-03-15 1997-07-01 Hyman; Edward Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array
US5299137A (en) * 1990-04-05 1994-03-29 Vlsi Technology, Inc. Behavioral synthesis of circuits including high impedance buffers
US5544067A (en) * 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5428550A (en) * 1990-06-28 1995-06-27 National Semiconductor Corporation Hierarchical hardware flowchart using symbolic macros
US5490232A (en) * 1990-10-25 1996-02-06 Daiwa House Industry Co., Ltd. Computer-aided thought process simulation design system
US5661661A (en) * 1990-12-21 1997-08-26 Synopsys, Inc. Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof
US5193180A (en) * 1991-06-21 1993-03-09 Pure Software Inc. System for modifying relocatable object code files to monitor accesses to dynamically allocated memory
US5305437A (en) * 1991-09-03 1994-04-19 International Business Machines Corporation Graphical system descriptor method and system
EP0532792B1 (de) * 1991-09-20 1997-11-19 Siemens Aktiengesellschaft Digitale Fernmeldevermittlungsanlage
JP2760682B2 (ja) * 1991-09-30 1998-06-04 株式会社東芝 ハードウェアの設計支援システム
US5329178A (en) * 1991-11-27 1994-07-12 North American Philips Corporation Integrated circuit device with user-programmable conditional power-down means
US5491640A (en) * 1992-05-01 1996-02-13 Vlsi Technology, Inc. Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication
US5325204A (en) * 1992-05-14 1994-06-28 Hitachi America, Ltd. Narrowband interference cancellation through the use of digital recursive notch filters
US5400084A (en) * 1992-05-14 1995-03-21 Hitachi America, Ltd. Method and apparatus for NTSC signal interference cancellation using recursive digital notch filters
US5282023A (en) * 1992-05-14 1994-01-25 Hitachi America, Ltd. Apparatus for NTSC signal interference cancellation through the use of digital recursive notch filters
US5325188A (en) * 1992-05-14 1994-06-28 Hitachi America, Ltd. Apparatus for NTSC signal interference cancellation through the use of digital recursive notch filters
JP3184011B2 (ja) * 1992-07-20 2001-07-09 株式会社東芝 帯域圧縮信号処理装置
US5583650A (en) * 1992-09-01 1996-12-10 Hitachi America, Ltd. Digital recording and playback device error correction methods and apparatus for use with trick play data
US5623344A (en) * 1992-09-01 1997-04-22 Hitachi America, Ltd. Digital video recording device with trick play capability
JPH06149554A (ja) * 1992-11-09 1994-05-27 Matsushita Electric Ind Co Ltd プログラム動作仕様自動合成装置及びその方法
US5416719A (en) * 1992-12-17 1995-05-16 Vlsi Technology, Inc. Computerized generation of truth tables for sequential and combinatorial cells
US5444575A (en) * 1994-01-21 1995-08-22 Hitachi America, Ltd. Method for recording digital data using a set of heads including a pair of co-located heads to record data at a rate lower than the full recording rate possible using the set of heads
US5377051A (en) * 1993-01-13 1994-12-27 Hitachi America, Ltd. Digital video recorder compatible receiver with trick play image enhancement
US5576902A (en) * 1993-01-13 1996-11-19 Hitachi America, Ltd. Method and apparatus directed to processing trick play video data to compensate for intentionally omitted data
US5404319A (en) * 1993-02-11 1995-04-04 Analog, Inc. Translation of behavioral modeling properties into an analog hardware description language
US5557774A (en) * 1993-03-22 1996-09-17 Hitachi, Ltd. Method for making test environmental programs
JP2815281B2 (ja) * 1993-04-19 1998-10-27 株式会社ピーエフユー デジタル回路設計支援システムおよびその方法
US5465216A (en) * 1993-06-02 1995-11-07 Intel Corporation Automatic design verification
JPH0765040A (ja) * 1993-08-24 1995-03-10 Matsushita Electric Ind Co Ltd 機能データインターフェース方法および機能データインターフェース装置
EP0660268A3 (de) * 1993-10-15 1996-01-31 Cadence Design Systems Verfahren zur Darstellung eines elektronischen Modells.
US5548539A (en) * 1993-11-05 1996-08-20 Analogy, Inc. Analysis mechanism for system performance simulator
US5544071A (en) * 1993-12-29 1996-08-06 Intel Corporation Critical path prediction for design of circuits
US5426591A (en) * 1994-01-28 1995-06-20 Vlsi Technology, Inc. Apparatus and method for improving the timing performance of a circuit
US5541850A (en) * 1994-05-17 1996-07-30 Vlsi Technology, Inc. Method and apparatus for forming an integrated circuit including a memory structure
US5475605A (en) * 1994-05-26 1995-12-12 Cadence Design Systems, Inc. Timing analysis for logic optimization using target library delay values
US5613063A (en) * 1994-07-01 1997-03-18 Digital Equipment Corporation Method and apparatus for checking validity of memory operations
DE4426001A1 (de) * 1994-07-22 1996-02-01 Sel Alcatel Ag Verfahren zur Überlastvermeidung bei einem Systemanlauf eines Mehrrechnersystems und Mehrrechnersystem dafür
US5539680A (en) * 1994-08-03 1996-07-23 Sun Microsystem, Inc. Method and apparatus for analyzing finite state machines
US5572712A (en) * 1994-09-30 1996-11-05 Vlsi Technology, Inc. Method and apparatus for making integrated circuits with built-in self-test
US5638291A (en) * 1994-10-14 1997-06-10 Vlsi Technology, Inc. Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew
US5586046A (en) * 1994-10-28 1996-12-17 Motorola, Inc. Computer implemented method for generating an integrated circuit design
US5533179A (en) * 1994-12-01 1996-07-02 Motorola, Inc. Apparatus and method of modifying hardware description language statements
US5537580A (en) * 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5568200A (en) * 1995-06-07 1996-10-22 Hitachi America, Ltd. Method and apparatus for improved video display of progressively refreshed coded video
ATE257611T1 (de) * 1995-10-23 2004-01-15 Imec Inter Uni Micro Electr Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software

Also Published As

Publication number Publication date
JP2001522084A (ja) 2001-11-13
EP1025492A1 (de) 2000-08-09
IL135810A0 (en) 2001-05-20
US5949993A (en) 1999-09-07
EP1025492B1 (de) 2003-04-02
KR20010024576A (ko) 2001-03-26
WO1999023555A1 (en) 1999-05-14
CA2307777A1 (en) 1999-05-14
DE69812990T2 (de) 2004-06-17
AU1290699A (en) 1999-05-24
DE69812990D1 (de) 2003-05-08

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