ATE225965T1 - Verfahren zur erzeugung von anwendungspezifischen integrierten schaltungen unter verwendung einer programmierbaren hardware-architektur - Google Patents
Verfahren zur erzeugung von anwendungspezifischen integrierten schaltungen unter verwendung einer programmierbaren hardware-architekturInfo
- Publication number
- ATE225965T1 ATE225965T1 AT98960362T AT98960362T ATE225965T1 AT E225965 T1 ATE225965 T1 AT E225965T1 AT 98960362 T AT98960362 T AT 98960362T AT 98960362 T AT98960362 T AT 98960362T AT E225965 T1 ATE225965 T1 AT E225965T1
- Authority
- AT
- Austria
- Prior art keywords
- specific integrated
- hardware architecture
- integrated circuit
- integrated circuits
- programmable hardware
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
- Logic Circuits (AREA)
- Devices For Executing Special Programs (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/980,631 US6075935A (en) | 1997-12-01 | 1997-12-01 | Method of generating application specific integrated circuits using a programmable hardware architecture |
PCT/US1998/024909 WO1999028840A1 (en) | 1997-12-01 | 1998-11-24 | Method of generating application specific integrated circuits using a programmable hardware architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE225965T1 true ATE225965T1 (de) | 2002-10-15 |
Family
ID=25527722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT98960362T ATE225965T1 (de) | 1997-12-01 | 1998-11-24 | Verfahren zur erzeugung von anwendungspezifischen integrierten schaltungen unter verwendung einer programmierbaren hardware-architektur |
Country Status (8)
Country | Link |
---|---|
US (2) | US6075935A (de) |
EP (1) | EP1034495B1 (de) |
JP (1) | JP2002503839A (de) |
KR (1) | KR20010032633A (de) |
AT (1) | ATE225965T1 (de) |
DE (1) | DE69808665T2 (de) |
HK (1) | HK1030664A1 (de) |
WO (1) | WO1999028840A1 (de) |
Families Citing this family (81)
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US5966534A (en) * | 1997-06-27 | 1999-10-12 | Cooke; Laurence H. | Method for compiling high level programming languages into an integrated processor with reconfigurable logic |
EP1645956A3 (de) * | 1997-08-29 | 2008-02-13 | Matsushita Electric Industrial Co., Ltd. | Anordnung zur Befehlsumwandlung um der Anzahl von Befehlsarten zu reduzieren |
US8686549B2 (en) * | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
US6075935A (en) * | 1997-12-01 | 2000-06-13 | Improv Systems, Inc. | Method of generating application specific integrated circuits using a programmable hardware architecture |
DE19861088A1 (de) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Verfahren zur Reparatur von integrierten Schaltkreisen |
JPH11296381A (ja) | 1998-04-08 | 1999-10-29 | Matsushita Electric Ind Co Ltd | 仮想マシン及びコンパイラ |
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US8230411B1 (en) | 1999-06-10 | 2012-07-24 | Martin Vorbach | Method for interleaving a program over a plurality of cells |
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US6694491B1 (en) | 2000-02-25 | 2004-02-17 | Lightspeed Semiconductor Corporation | Programmable logic array embedded in mask-programmed ASIC |
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US20010025363A1 (en) * | 2000-03-24 | 2001-09-27 | Cary Ussery | Designer configurable multi-processor system |
JP2004506261A (ja) | 2000-06-13 | 2004-02-26 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | パイプラインctプロトコルおよびct通信 |
JP3813414B2 (ja) * | 2000-06-26 | 2006-08-23 | 東芝マイクロエレクトロニクス株式会社 | Asic設計支援システム |
JP2002049652A (ja) * | 2000-08-03 | 2002-02-15 | Hiroshi Yasuda | デジタル回路設計方法、そのコンパイラーおよびシミュレータ |
US7055125B2 (en) | 2000-09-08 | 2006-05-30 | Lightspeed Semiconductor Corp. | Depopulated programmable logic array |
US20020089348A1 (en) * | 2000-10-02 | 2002-07-11 | Martin Langhammer | Programmable logic integrated circuit devices including dedicated processor components |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
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US20020116164A1 (en) * | 2001-01-19 | 2002-08-22 | El-Ghoroury Hussein S. | Matched instruction set processor systems and efficient design and implementation methods thereof using java programming language |
US20020112219A1 (en) * | 2001-01-19 | 2002-08-15 | El-Ghoroury Hussein S. | Matched instruction set processor systems and efficient design and implementation methods thereof |
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US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US9436631B2 (en) | 2001-03-05 | 2016-09-06 | Pact Xpp Technologies Ag | Chip including memory element storing higher level memory data on a page by page basis |
US9141390B2 (en) | 2001-03-05 | 2015-09-22 | Pact Xpp Technologies Ag | Method of processing data with an array of data processors according to application ID |
US9552047B2 (en) | 2001-03-05 | 2017-01-24 | Pact Xpp Technologies Ag | Multiprocessor having runtime adjustable clock and clock dependent power supply |
US9411532B2 (en) | 2001-09-07 | 2016-08-09 | Pact Xpp Technologies Ag | Methods and systems for transferring data between a processing device and external devices |
US9250908B2 (en) | 2001-03-05 | 2016-02-02 | Pact Xpp Technologies Ag | Multi-processor bus and cache interconnection system |
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US10031733B2 (en) * | 2001-06-20 | 2018-07-24 | Scientia Sol Mentis Ag | Method for processing data |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
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US8686475B2 (en) * | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
EP1476221A4 (de) * | 2002-02-01 | 2008-04-23 | Cleveland Clinic Foundation | Verstellbare simulierungsvorrichtung und verwendungsverfahren dafür |
US20030171907A1 (en) * | 2002-03-06 | 2003-09-11 | Shay Gal-On | Methods and Apparatus for Optimizing Applications on Configurable Processors |
US9170812B2 (en) | 2002-03-21 | 2015-10-27 | Pact Xpp Technologies Ag | Data processing system having integrated pipelined array data processor |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US20110161977A1 (en) * | 2002-03-21 | 2011-06-30 | Martin Vorbach | Method and device for data processing |
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US7394284B2 (en) | 2002-09-06 | 2008-07-01 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
US7167908B2 (en) * | 2002-09-27 | 2007-01-23 | Intel Corporation | Facilitating operation of a multi-processor system via a resolved symbolic constant |
US7107568B2 (en) * | 2002-10-07 | 2006-09-12 | Hewlett-Packard Development Company, Lp. | System and method for reducing wire delay or congestion during synthesis of hardware solvers |
US8276135B2 (en) * | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
US7310594B1 (en) * | 2002-11-15 | 2007-12-18 | Xilinx, Inc. | Method and system for designing a multiprocessor |
US7010666B1 (en) * | 2003-01-06 | 2006-03-07 | Altera Corporation | Methods and apparatus for memory map generation on a programmable chip |
SE0300742D0 (sv) * | 2003-03-17 | 2003-03-17 | Flow Computing Ab | Data Flow Machine |
JP2006524850A (ja) * | 2003-04-04 | 2006-11-02 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | データ処理方法およびデータ処理装置 |
US20070186076A1 (en) * | 2003-06-18 | 2007-08-09 | Jones Anthony M | Data pipeline transport system |
KR20060063800A (ko) | 2003-06-18 | 2006-06-12 | 앰브릭, 인크. | 집적 회로 개발 시스템 |
US20070277161A1 (en) * | 2004-03-04 | 2007-11-29 | Trustees Of Boston University | System and Method for Programmable Logic Acceleration of Data Processing Applications and Compiler Therefore |
US20050283756A1 (en) * | 2004-06-22 | 2005-12-22 | Intel Corporation | Method and system to automatically generate performance evaluation code for multi-threaded/multi-processor architectures |
US7278122B2 (en) * | 2004-06-24 | 2007-10-02 | Ftl Systems, Inc. | Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization |
US20060095894A1 (en) * | 2004-09-15 | 2006-05-04 | Wilde Myles J | Method and apparatus to provide graphical architecture design for a network processor having multiple processing elements |
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US8898633B2 (en) * | 2006-08-24 | 2014-11-25 | Siemens Industry, Inc. | Devices, systems, and methods for configuring a programmable logic controller |
JP2008060653A (ja) * | 2006-08-29 | 2008-03-13 | Matsushita Electric Ind Co Ltd | 制御装置 |
WO2009062496A1 (de) * | 2007-11-17 | 2009-05-22 | Pact Xpp Technologies Ag | Rekonfiguri erbare fliesskomma- und bit- ebenen datenverarbeitungseinheit |
DE112008003670A5 (de) * | 2007-11-28 | 2010-10-28 | Pact Xpp Technologies Ag | Über Datenverarbeitung |
US20110119657A1 (en) * | 2007-12-07 | 2011-05-19 | Martin Vorbach | Using function calls as compiler directives |
US8407515B2 (en) * | 2008-05-06 | 2013-03-26 | International Business Machines Corporation | Partition transparent memory error handling in a logically partitioned computer system with mirrored memory |
US9009662B2 (en) * | 2008-12-18 | 2015-04-14 | Adobe Systems Incorporated | Platform sensitive application characteristics |
US9009661B2 (en) * | 2008-12-18 | 2015-04-14 | Adobe Systems Incorporated | Platform sensitive application characteristics |
US8904366B2 (en) * | 2009-05-15 | 2014-12-02 | International Business Machines Corporation | Use of vectorization instruction sets |
US9553590B1 (en) | 2012-10-29 | 2017-01-24 | Altera Corporation | Configuring programmable integrated circuit device resources as processing elements |
US10452392B1 (en) | 2015-01-20 | 2019-10-22 | Altera Corporation | Configuring programmable integrated circuit device resources as processors |
US10891132B2 (en) * | 2019-05-23 | 2021-01-12 | Xilinx, Inc. | Flow convergence during hardware-software design for heterogeneous and programmable devices |
US10891414B2 (en) | 2019-05-23 | 2021-01-12 | Xilinx, Inc. | Hardware-software design flow for heterogeneous and programmable devices |
US11188312B2 (en) | 2019-05-23 | 2021-11-30 | Xilinx, Inc. | Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices |
US11301295B1 (en) | 2019-05-23 | 2022-04-12 | Xilinx, Inc. | Implementing an application specified as a data flow graph in an array of data processing engines |
US10977018B1 (en) | 2019-12-05 | 2021-04-13 | Xilinx, Inc. | Development environment for heterogeneous devices |
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-
1997
- 1997-12-01 US US08/980,631 patent/US6075935A/en not_active Expired - Lifetime
-
1998
- 1998-11-24 KR KR1020007005911A patent/KR20010032633A/ko active IP Right Grant
- 1998-11-24 WO PCT/US1998/024909 patent/WO1999028840A1/en active IP Right Grant
- 1998-11-24 EP EP98960362A patent/EP1034495B1/de not_active Expired - Lifetime
- 1998-11-24 AT AT98960362T patent/ATE225965T1/de not_active IP Right Cessation
- 1998-11-24 JP JP2000523617A patent/JP2002503839A/ja not_active Withdrawn
- 1998-11-24 DE DE69808665T patent/DE69808665T2/de not_active Expired - Fee Related
-
2000
- 2000-01-10 US US09/480,087 patent/US6484304B1/en not_active Expired - Lifetime
-
2001
- 2001-02-28 HK HK01101478A patent/HK1030664A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2002503839A (ja) | 2002-02-05 |
DE69808665T2 (de) | 2003-07-03 |
US6484304B1 (en) | 2002-11-19 |
WO1999028840A1 (en) | 1999-06-10 |
HK1030664A1 (en) | 2001-05-11 |
DE69808665D1 (de) | 2002-11-14 |
EP1034495A1 (de) | 2000-09-13 |
KR20010032633A (ko) | 2001-04-25 |
EP1034495B1 (de) | 2002-10-09 |
US6075935A (en) | 2000-06-13 |
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