WO2001071490A2

WO2001071490A2 - A software configurable input/output module

Info

Publication number: WO2001071490A2
Application number: PCT/US2001/006307
Authority: WO
Inventors: Oz Levia; Raymond Ryan; Cary Ussery
Original assignee: Improv Systems, Inc.
Priority date: 2000-03-23
Filing date: 2001-02-28
Publication date: 2001-09-27
Also published as: AU2001241819A1; WO2001071490A3

Abstract

The invention relates to a software configurable input/output module for an Application Specific Integrated Circuit (ASIC). The I/O module serves as a programmable interface between a plurality of task engines and a plurality of external devices and includes a pre-defined set of resources and interconnections between those resources which are used to implement I/O protocols. The I/O module is programmed through a set of internal programmable configuration registers which are written to by one or more initialization tasks executing on a connected task engine. Once these programmable configuration registers are written to, the I/O module responds to data and control signals in a defined manner. The programmable configuration registers enable the selection and combination of these pre-defined resources to implement specific I/O protocols used for the communication of data and control between external devices and task engines.

Description

A Software Configurable Input/Output Module

Cross Reference to Related Case

This claims priority to and the benefit of U.S. Provisional Patent Application Serial No.

60/191,403 filed March 23, 2000, the entirety of which is hereby incorporated by reference.

Technical Field The invention relates generally to the field of input/output modules. In particular, the

invention relates to a software configurable fixed hardware architecture input/output module in

an ASIC.

Background

Custom integrated circuits are widely used today in the electronics industry. The demand

for custom integrated circuits is rapidly increasing because of a dramatic growth in the demand

for highly specific consumer electronics and a trend towards increased product functionality. In

addition, the use of custom integrated circuits is advantageous because such custom circuits reduce system complexity and, therefore, lower manufacturing costs, increase reliability, and

increase system performance.

There are numerous types of custom integrated circuits. One type consists of

programmable logic devices (PLDs) including field programmable gate arrays (FPGAs). FPGAs are programmed by the end user using special-purpose equipment. Programmable logic devices

are, however, undesirable for many applications because they operate at relatively slow speeds, have a relatively low capacity, and have relatively high cost per chip.

Another type of custom integrated circuit consists of application-specific integrated

circuits (ASICs) including gate-array based and cell-based ASICs which are often referred to as

"semi-custom" ASICs. Semi-custom ASICs are programmed by either defining the placement and interconnection of a collection of predefined logic cells which are used to create a mask for manufacturing the IC (cell-based) or defining the final metal interconnection layers to lay over a predefined pattern of transistors on the silicon (gate-array-based). Semi-custom ASICs can achieve high performance and high integration but can be undesirable because they have relatively high design costs, have relatively long design cycles (the time it takes to transform a defined functionality into a mask), and relatively low predictability of integrating into an overall electronic system.

Another type of custom integrated circuit is referred to as application-specific standard parts (ASSPs) which are non-programmable integrated circuits that are designed for specific applications. These devices are typically purchased off-the-shelf from integrated circuit suppliers. ASSPs have predetermined architectures and input and output interfaces. They are typically designed for specific products and, therefore, have short product lifetimes.

Yet another type of custom integrated circuit is referred to as a software-only design. ■ This type uses a general purpose processor and a high-level compiler. The end user programs the desired functions with a high-level language. The compiler generates the machine code that instructs the processor to perform the desired functions. Software-only designs typically require general-purpose hardware to perform the desired function. In addition, software only designs have relatively poor performance because the hardware is not optimized to perform the desired functions. Summary of the Invention

The invention relates to a software configurable fixed hardware architecture input/output module in an ASIC. One aspect of the invention relates to an input/output module for use with a plurality of task engines. The input/output module includes a plurality of data paths each electrically connected to one or more of a plurality of resources. The plurality of data paths are pre-defined and the data-flow of the plurality of data paths is determined by one of the plurality s of task engines under program control. The input/output module also includes a plurality of control paths each electrically connected to one or more of the plurality of resources. The plurality of control paths are pre-defined and the control-flow of the plurality of control paths is determined by one of the plurality of task engines under program control.

In one embodiment, the data-flow of the plurality of datapaths corresponds to inbound data originating from at least one device external to the input/output module and transmitted to at least one of the plurality of task engines. In another embodiment, the data-flow of the plurality of data paths corresponds to outbound data originating from at least one of the plurality of task engines and transmitted to at least one device external to the input/output module.

In another embodiment, the control-flow of the plurality of control paths corresponds to inbound data originating from at least one device external to the input/output module and transmitted to a control unit internal to the input/output module. In another embodiment, the control-flow of the plurality of control paths corresponds to outbound data originating from at least one of the plurality of task engines and transmitted to a control unit internal to the input/output module.

In still other embodiments, the input/output module includes at least one programmable state machine comprising a plurality of pre-defined input signals, a plurality of pre-defined output signals, and a plurality of programmable states. Each programmable state comprises a plurality of programmable state transitions and a plurality of output signal values. The plurality of programmable state transitions are programmed through a plurality of transition terms and each of the plurality of transition terms is computed using a logical combination of at least one of the plurality of pre-defined state machine input signals. Additionally, the logical combination of at least one of the plurality of pre-defined state machine input signals is programmable. In another embodiment, at least one programmable state machine controls the transfer of data and control between the input/output module and an external device according to a defined transfer protocol. Additionally, at least one programmable state machine controls the sequencing of the transfer of data and control between the input/output module and the external device. In other embodiments, the input/output module includes a programmable control interface in communication with at least one of the plurality of task engines. The programmable control interface includes a programmable table. The programmable table includes task queue transactions which are used with a bus for communication of control with at least one of the plurality of task engines. The programmable control interface facilitates communication of control between any of the plurality of task engines and the input/output module.

In still other embodiments, the input/output module includes a memory mapped data interface in communication with at least one of the plurality of task engines. The memory mapped data interface facilitates data transfers to and from the input/output module.

In another embodiment, the input/output module includes a control data register which facilitates communication of control data between the programmable state-machines, the external device, and the plurality of task engines. The input/output module also includes a programmable register which controls accesses to the control data register.

Another aspect of the invention relates to a method of controlling data flow into and out of an input/output module in communication with one or more external devices, at least one task engine, and a bus. The method comprises loading a program into at least one task engine and transferring data between the input/output module, one or more external devices, at least one task engine, and the data bus in response to the program in the task engine. In one embodiment, the method further comprises transferring data between the input/output module, one or more external devices, at least one task engine, and the data bus according to a defined data transfer protocol.

In another embodiment, the method further comprises providing at least one

programmable state machine internal to the input/output module for controlling the sequencing of the transfer of data between the input/output module, one or more external devices, at least one task engine, and the data bus. The state machine comprises a plurality of pre-defined input signals, a plurality of pre-defined output signals, and a plurality of programmable states. Each of the programmable states comprises a plurality of programmable state transitions and a plurality of output signals. The plurality of programmable state transitions are programmed through a plurality of transition terms and each of the plurality of transition terms is computed using a logical combination of at least one of the plurality of pre-defined state machine input signals. The logical combination of at least one of the plurality of pre-defined state machine input signals is programmable. In another embodiment, the method further comprises transferring data and control between the input/output module, one or more external devices, at least one task engine, and the data bus according to a defined data transfer protocol.

Still another aspect of the invention relates to an input/output module for use with a plurality of task engines which are in communication with a bus. The input/output module includes a first input/output port for communication with at least one external device, a second input/output port for communication with one of a plurality of task engines, and a third input/output port for communication with the bus. A data stream moves between each of the ports under program control by one of the plurality of task engines. In one embodiment, a program is stored on one of the plurality of task engines. In another embodiment, the second input/output port is in communication with one of a plurality of shared memory modules through

one of the plurality of task engines. The one of the plurality of shared memory modules provides a communication path between one of the plurality of task engines and a second of the plurality

of task engines.

Brief Description of the Drawings

The invention is pointed out with particularity in the appended claims. The above and

further advantages of the invention may be better understood by referring to the following

description in conjunction with the accompanying drawings, which are not necessarily to scale

because the emphasis is on conveying the concepts of the invention and in which:

Fig. 1 is a block diagram illustrative of an embodiment of the hardware components of a device constructed in accordance with the invention;

Fig. 2 is a block diagram illustrative of an embodiment of a software configurable fixed hardware architecture input/output module constructed according to the present invention and

shown in Fig. 1 ;

Fig. 3 is a block diagram illustrative of an embodiment of a pair of parallel interface

units and a parallel interface control unit in the input/output module shown in Fig. 2;

Fig. 4 is a block diagram illustrative of an embodiment of a pair of serial interface units

and a serial interface control unit in the input/output module shown in Fig. 2;

Fig. 5 is a block diagram illustrative of an embodiment of a programmable state machine

in the parallel interface unit shown in Fig. 3; and

Fig. 6 is a block diagram illustrative of an embodiment of a programmable state machine in the serial interface unit shown in Fig. 4. Detailed Description

Referring to Fig. 1, one embodiment of the programmable system architecture circuit

(PSA) 100 is an application specific integrated circuit (ASIC). The PSA is a software configurable fixed hardware architecture that includes a plurality of task engines 120, shared memories 112, a queue bus 124, an input/output module 108 (I/O module), and pin modules 104, all of which are interconnected by pre-defined data and control paths. Specifically, the pin module 104 includes pins that can be programmed to be input, output, bi-directional, or output enabled. The pin module 104 is in communication with the I/O module 108, which is in turn, in communication with the queue bus 124 and at least one task engine 120. Each task engine 120 is in communication with at least one shared memory 112 and the queue bus 124.

The task engines 120 are high performance processors that are programmed using Very Long Instruction Word (VLIW) instructions. Each NLIW instruction includes a set of micro- operations where each micro-operation specifies an individual operation of a task engine 120. The task engines 120 communicate with each other through the shared memory modules 112 or over the queue bus 124. The shared memory modules 112 are typically random-access memories (RAM) that can be written to and read from by the task engines 120. At least one task engine 120 can communicate directly with the I/O module 108. Task engines 120 and the I/O module 108 use the queue bus 124 to schedule (queue) the execution of tasks on the task engines 120 or the I/O module 108. The tasks that execute on a task engine 120 include sequences of NLIW instructions. The VLIW instructions are read from the task engine 120 internal program memory. The program memory may be implemented by a combination of non-volatile read only memory (ROM) and volatile RAM memory.

The I O module 108 serves as a programmable interface between the pin module 104 and the task engines 120. The I/O module 108 is programmed through a set of programmable configuration registers contained within the I/O module 108. The programmable configuration registers are volatile and are written to by one or more initialization tasks executing on a connected task engine 120. Once these programmable configuration registers are written to, the units within the I/O module 108 respond to data and control signals in a defined manner. Programming the I/O module 108 to function in a defined manner facilitates the implementation

of specific I/O protocols used for the communication of data and control between external devices (through the pins in the pin module 104) and task engines 120. Furthermore, the I/O module 108 is not generally programmable in the sense of a processor, but rather includes a predefined set of resources and interconnections between those resources which are used to implement I/O protocols. The programmable configuration registers enable the selection and combination of these pre-defined resources to implement specific I/O protocols. Additionally, the I/O Module 108 includes programmable state-machines 302, 402 that enable the implementation of control sequences associated with these I/O protocols. The programmable state-machines 302, 402 are not general purpose state-machines, but rather are constrained with a set of pre-defined input and output signals which are used to control the pre-defined resources within the I/O module 108.

In one embodiment, the non- volatile program memory (ROM) of a task engine 120 stores a first initialization task that programs the I/O module 108 to implement a specific I/O protocol for communication with external ROM. Programming the I/O module 108 involves at least the first initialization task writing to the various programmable configuration registers in the I/O module 108. The first initialization task is executed following system reset (when the system powers up). After the I/O module 108 is programmed, the first initialization task queues a second initialization task (also stored in the internal ROM). The second initialization task instructs the task engine 120 to communicate with the external ROM (through the I/O module 108) to read program data from the external ROM and write this data to the volatile program memories (RAM) within the task engines 120. Finally, this second initialization task queues an additional initialization task within the volatile program RAM (i.e. a task is read in from the external ROM). This additional initialization task may instruct the task engine 120 to program the I/O module 108 for additional I/O protocols and this additional initialization task may also instruct the task engine 120 to initiate an application program.

Fig. 2 is a block diagram of an embodiment of the software configurable fixed hardware architecture I/O module 108 of Fig 1. This embodiment of the I/O module 108 includes parallel interface units A 204 and B 206, a parallel control unit C 208, serial interface units A 210 and B 212, a serial control unit C 214, a task scheduler unit 216, a timer unit 218, an I/O task queue unit 220, and two task engine interface units 222. All of these units are interconnected by predefined data and control paths.

In an another embodiment of the I/O module 108, the I/O module 108 includes a parallel group and a serial group. The parallel group includes a parallel control unit C 208 and parallel interface units A 204 and B 206. The serial group includes a serial interface control unit C 214 and serial interface units A 210 and B 212. Other embodiments of the I/O module 108 include a task scheduler 216, an I/O task queue 220, a timer unit 218, two task engine interface units 222, multiple parallel groups, and multiple serial groups. An important characteristic of the architecture of the I/O module 108 is that it is scaleable, which allows different embodiments of the I/O module 108 to include different numbers of serial and parallel groups.

The task scheduler unit 216 and I/O task queue 220 allow the I/O module 108 to interface with the queue bus 124. The task scheduler 216 is in communication with the queue bus 124 and writes task queue transactions to the queue bus 124. A task queue transaction schedules a task (operation) for execution by one of the task engines 120 or the I/O module 108. The task scheduler 216 includes a programmable task table which contains task queue transactions. These task queue transactions define the set of tasks (operations) that can be written to the queue bus

124 from the I/O module 108. In one embodiment, the task table entries are written to the task table by a program stored and executed on a task engine 120.. The task scheduler unit 216 is also in communication with the parallel interface units A 204 and B 206, the serial interface units A

210 and B 212, and the timer unit 218. These units can request the task scheduler 216 to write an entry from the programmable task table to the queue bus 124. In another embodiment, this programmable task table is divided into an 'A' section with capacity for seven task queue entries and a 'B' section with capacity for seven task queue entries. The task table entries in the 'A' section can only be requested by the parallel interface unit A 204 or the serial interface unit A 210, and table entries in the 'B' section can only be requested by the parallel interface unit B 206 or the serial interface unit B 212. In another embodiment, the task scheduler unit 216 maintains a request flag for each entry in the programmable task table. The request flag is set when a request to write a programmable task table entry to the queue bus 124 is received from another unit in the I/O module 108. The request flag is cleared when the task scheduler unit 216 places the corresponding programmable task table entry on the queue bus 124. The task scheduler unit

216 also arbitrates with the task engines 120 for usage of the queue bus 124.

The I/O task queue 220 is a fixed, non-programmable interface for tasks queued to the I/O module 108 from the queue bus 124. The I/O task queue 220 monitors the queue bus 124 and performs tasks queued to the I/O module 108 over the queue bus 124. The set of tasks that may be queued to the I/O module 108 (and performed by the I/O task queue 220) are predefined. These tasks include tasks to set the bits of the task register 312, 412 within each parallel control unit C 208 and serial control unit C 214, and three timer control tasks (start, stop, and reset) to control each timer within the timer unit 218. The I/O task queue 220 is in communication with - li the parallel control unit C 208, the serial control unit C 214, the queue bus 124, and the timer unit 218.

The timer unit 218 includes a collection of individual timers and a programmable configuration register. The timers are used to implement timed or periodic control. Timers are also used in conjunction with the task scheduler unit 216 to queue tasks. In one embodiment, each timer has a fixed association with a programmable task table entry in the task scheduler unit

216 in that each timer has a fixed entry in the programmable task table. The timer unit 218 can request that the task scheduler unit 216 write the fixed entry to the queue bus 124. As mentioned

above, there are three timer control tasks (start, stop, and reset) to control each timer within the timer unit 218. Each of the control operations for each timer (start, stop, and reset) is implemented through a corresponding pre-defined I/O task. The programmable configuration register is used to define the reset value (which determines the period of the timer) and the operating mode (which is either repeated or single step operation). Programming the timer unit 218 involves at least the first initialization task writing to the programmable configuration register in the time unit 218 following system reset. The timer unit 218 is in commimication with the task scheduler unit 216, the I/O task queue 220, and the task engine interface units 222. Each task engine interface unit 222 provides a memory mapped communication interface between the I/O module 108 and a connected task engine 120. Each task engine interface unit 222 supports simultaneous read and write operations. In one embodiment, the task engine interface unit 222 allows a task engine 120 to read a data value from a FIFO (First In First Out) queue 306 in the parallel interface units A 204 or B 206, read a data value from the FIFO queue 406 in the serial interface units A 210 or B 212, and directly read the value of a set of data pins 226, 234 connected to a parallel interface unit A 204 or B 206. In another embodiment, the task engine interface unit 222 allows a task engine 120 to write a data value to the FIFO queue 306 in the parallel interface units A 204 or B 206, write a data value to the FIFO queue 406 in the serial interface units A 210 or B 212, and directly write the value of a set of data pins 226, 234 connected to the parallel interface units A 204 or B 206. In still another embodiment, the task engine interface unit 222 also allows a task engine 120 to read the data value of a set of bits in the control register 310, 410 within a parallel control unit C 208 or serial control unit C 214, write selected bits of the control register 310, 410 within the parallel control unit C 208 or the serial control unit C 214, and write to a programmable configuration register within one of the units within the I/O module 108. In one embodiment, the addresses associated with I/O read/write operations are decoded to determine the data being accessed and the I/O units within the I/O module 108 to/from which data is communicated. Each task engine interface unit 222 is in communication with a task engine 120 and all the units within the I/O module 108.

Parallel interface units A 204 and B 206 are used in the implementation of high-speed parallel data communication. In one embodiment, parallel interface unit A 204 is connected to thirty-two bi-directional data pins 226 and parallel interface unit B is connected to sixteen bi-

directional data pins 234. The incoming or outgoing data on the data pins 226, 234 can be either passed through a FIFO queue 306 or accessed directly by a task engine 120 through the task engine interface unit 222. Each parallel interface unit A 204 and B 206 is also in communication with a parallel interface control unit C 208, and the task scheduler unit 216.

Serial interface units A 210 and B 212 are used in the implementation of a serial data communication. Both serial interface units A 210 and B 212 are in communication with a serial interface control unit C 214, the task engine interface units 222, and the task scheduler unit 216. Serial interface units A 210 and B 212 are also connected to four bi-directional pins 236, 244. The incoming or outgoing data on the data pins 236, 244 can be either passed through a FIFO queue 406 or accessed directly by a task engine 120 through a task engine interface unit 222. The parallel interface control unit C 208 and the serial interface control unit C 214 are used for communicating control signals. Parallel interface control unit C 208 supports communication of control signals to and from eight bi-directional control pins 230, task engines

120, and parallel interface units A 204 and B 206. Serial interface control unit C 214 supports communication of control signals to and from eight bi-directional control pins 240, task engines

120, and serial interface units A 210 and B 212. Additionally, there are two sets of four auxiliary output pins 228, 232. The auxiliary output pins 228 are shared between the parallel interface unit

A 204 and the serial interface unit A 210. The auxiliary output pins 232 are shared between the parallel interface unit B 206 and the serial interface unit B 212. These auxiliary output pins 228, 232 are used if additional output control pins are required by a particular interface.

Fig. 3 is a block diagram illustrative of an embodiment of the parallel interface units A 204 and B 206, and the parallel interface control unit C 208 in the I/O module 108 shown in Fig. 2. Referring to Figs. 2 and 3, the parallel interface units A 204 and B 206 are used in the implementation of high-speed parallel data communication. Each parallel interface unit A 204 and B 206 contains a pin register 304, a shift register 308, a FIFO queue 306, a programmable state-machine 302, and a programmable configuration register. The FIFO queue 306 is used to buffer data between the data pins 226, 234 and the task engine interface unit 222. The programmable state-machine 302 is used to implement the control associated with an I/O protocol. The shift register 308 is used to further buffer and synchronize data flowing between the FIFO queue 306 and the data pins 226, 234. The pin register 304 is used to buffer output data written directly from a task engine 120 through a task engine interface 222.

Parallel interface units A 204 and B 206 are connected to a single parallel interface control unit C 208. The parallel control unit C 208 facilitates the communication of control data and provides a means for this control data to be exchanged between the parallel interface units A and B 206, the set of control pins 230, the I/O task queue 22P, and a task engine 120 (through a task engine interface unit 222).

In one embodiment, parallel interface unit A 204 has a data width of thirty-two bits and parallel interface unit B 206 has a data width of sixteen bits. The data width of parallel interface units A 204 and B 206 determines the number of connected data pins 226, 234 and the width of the associated FIFO queue 306. Both parallel interface units A 204 and B 206 support data transfer between data pins 226, 234 and the task engines 120 (through a task engine interface unit

222). This data transfer (read/write) can be either directly between data pins 226, 234 and a task engine 120 or buffered through the FIFO queue 306. Data communication between the FIFO queue 306 and the data pins 226, 234 is controlled by the programmable state-machine 302 and is synchronized to an external application clock signal 248. The execution of a program by a task engine 120 controls data transfers between the task engines 120 and either the FIFO queue 306 or the data pins 226, 234. These data transfers are synchronized with an internal system clock signal 252. As mentioned above, each parallel interface unit A 204 and B 206 contains a programmable configuration register, which is used to configure the operation of each of the data pins 226,234. Each of the individual data pins 236, 234 can be configured for input, output, or bi-directional operation, and whether the values written to an output pin are from the pin register 304 or from the shift register 308. Configuring the data pins 236, 234 involves at least the first initialization task writing to the programmable configuration register in each parallel interface unit A 204 and B 206 following system reset. Data transferred between the data pins 226, 234 and the FIFO queue 306 is buffered and synchronized through the shift register 308. The shift register 308 can be used to pack pin data prior to transfer to the FIFO queue 306 from the data pins 226, 234 or to unpack FIFO data prior to transfer to the data pins 226, 234 from the FIFO queue 306. The data transfers are controlled by the programmable state-machine 302 and the programmable configuration register. On each application clock cycle, the programmable state- machine 302 controls whether no data transfer occurs, whether an outgoing transfer occurs, or whether an incoming transfer occurs. The programmable configuration register is used to select the options for packing and unpacking data.

The FIFO queue 306 is a (First In First Out) data buffer used for the temporary storage of data. It is used to buffer data (on the data pins 226, 234) communicated to/from a task engine 120 through a task engine interface unit 222. The FIFO queue 306 can be used either as an input queue for the transfer of data from the data pins 226, 234 to a task engine 120 through a task engine interface unit 222 or as an output queue for the transfer of data to the data pins 226, 234 from a task engine 120 through a task engine interface unit 222. The FIFO queue 306 includes an ordered list of entries. Data is written to the end of the list and read from the front of the list. The FIFO queue depth determines the maximum number of entries in the queue. In one embodiment, the FIFO queue 306 has a depth of thirty-two entries. In another embodiment, the FIFO queue 306 has a dedicated read port and a dedicated write port. Both ports can be used simultaneously. A write operation appends a new entry to the end of the FIFO queue 306 and a read operation removes the entry from the front of the FIFO queue 306. In another embodiment, the FIFO queue 306 is either in input mode or output mode. The programmable state-machine 302 controls the mode of the FIFO queue 306. When the FIFO queue 306 is in input mode, the task engine interface units 222 control the FIFO queue read port and the programmable state- machine 302 controls the FIFO queue write port. When the FIFO queue 306 is in output mode, the programmable state-machine 302 controls the FIFO queue read port and the task engine interface units 222 control the FIFO queue write port. A FIFO queue entry contains a data field, a count field, and a tag field. In still another embodiment, the width of the data field is thirty-two bits, the width of the count field is six bits, and the width of the tag field is two bits. The count and tag fields allow control information to be directly associated with a specific data entry. This control data is communicated between a task engine 120 and a programmable state-machine 302. The tag field can be used to mark specific entries (e.g. last entry of a block or a partial data word). The count field can be used with the programmable state-machine 302 to control state iterations, such as shifting serial data.

The FIFO queue 306 is also in communication with the programmable state-machine 302.

Fig. 5, is a diagram illustrative of an embodiment of a programmable state machine 302 in the parallel interface units A 204 and B 206. Referring to Figs. 3 and 5, the programmable state machine 302 includes a programming registers unit 510, a term computation unit 502, a state processing unit 504, a counter unit 506, and an I/O direction unit 508. The programmable

state-machine 302 is used to control a fixed set of I/O resources and/or to sequence a set of I/O operations (including data transfer operation and control operations) in accordance with an I/O protocol. Specifically, the programmable state-machine 302 controls the transfer of data between the parallel data pins 226, 234 and the FIFO queue 306. The programmable state machine 302 may also communicate control data with another programmable state-machine 302, a task engine ' 120, and/or an external controller through the connected parallel interface control unit C 208. The programmable state-machine 302 has a fixed set of available input signals and a fixed set of output signals. The programmable state-machine 302 also includes a set of programmable states. The operation of the programmable state-machine 302 is determined by writing to the programming registers unit 510 to define the state transitions and output signal values associated with each of the available states. These programmable registers 510 are written to (through the I/O interface unit 222) by an at least one initialization task executing on a task engine 120 following system reset.

In one embodiment, the programmable state-machines 302 controlling the parallel interface units A 204 and B 206 have nineteen predefined input signals. These input signals include eight control register bits and four task register bits from the parallel interface control unit C 208, two Tag bits and an Empty flag from the FIFO queue 306, and four terminal count flags from the counters in the counter unit 506.

In another embodiment, the programmable state-machines 302 controlling the parallel interface units A 204 and B 206 have forty-five pre-defined output signals. These output signals include eight bits controlling the four counters in the counter unit 506 (two control bits for each counter), three bits specifying a task table entry to be queued by the task scheduler unit 216, two Tag bits, two.bits from the I/O direction unit 508 to control the I/O direction, one FIFO-enable bit, one shift-enable bit, four auxiliary control bits, four set and four clear mask register bits, eight set and eight clear control register bits. Fig. 6 is a diagram illustrative of an embodiment of a programmable state machine 402 in the serial interface units A 210 and B 212. The programmable state machine 402 includes a programming registers unit 510, a term computation unit 502, a state processing unit 504, a counter unit 506, and an I/O direction unit 508. The programmable state machine 402 serves the same functions in the serial interface units A 210 and B 212 as the programmable state machine

302 serves in the parallel interface units A 202 and B 206 described above. Specifically, the programmable state-machine 402 controls the transfer of data between the serial data pins 236, 244 and the FIFO queue 406. The programmable state machine 402 may also communicate control data with another programmable state-machine 402, a task engine 120, and/or an external controller through the connected serial interface control unit C 214. The programmable state-machine 402 has a fixed set of available input signals and a fixed set of output signals. In one embodiment, the programmable state-machines 402 controlling the serial interface units A 210 and B 212 have twenty-one input signals which include eight control register bits and four task register bits from the serial interface control unit C 214, one Tag bit register and an Empty flag from the FIFO queue 406, four terminal count flags from the counters in the counter unit 506, two Match flags from the serial buffer 404, and a serial input bit [0]. In another embodiment, the programmable state-machines 402 controlling the serial interface units A 210 and B 212 have fifty pre-defined output signals including eight bits controlling the four counters in the counter unit 506 (two control bits for each counter), three bits which specify a task table entry to be queued by the task scheduler unit 216, two Tag bits, two bits for controlling the I/O direction unit 508, one FIFO-enable bit, one shift-enable bit, four auxiliary control bits, four set and four clear mask register bits, eight set and eight clear control register bits, one data select bit and four serial output bits.

In one embodiment, each programmable state-machine 302, 402 contains sixteen programmable states. The definition of each programmable state includes the specification of an ordered set of state-transition arcs and a set of signal values. There is one signal value for each programmable state-machine output signal (mentioned above). In one embodiment, each programmable state includes six state-transition arcs. A state-transition arc specifies a condition for the state transition from the current state to a target (next) state. The state-transition arc also specifies the target (next) state. The target-state may be any state including the current state. In a state-transition arc, the condition for transition to a next state is specified by a transition term. In one embodiment, there are twelve available transition terms (eleven programmable transition terms and one pre-defined transition term). The value of each programmable transition term is determined by a logical combination of the programmable state-machine input signals. Specifically, each of the first four transition terms (1-4) is computed by taking the logical AND of any three of the programmable state-machine inputs. Each of the next four transition terms (5-

8) is computed by taking the logical AND of any two of the programmable state-machine inputs. Each of the next three transition terms (9-11) is computed from any one of the programmable state-machine inputs. As a result of this computation, each of the transition terms (1-11) will either be a logical true or a logical false. Term 0 is predefined to always be logical true.

This method of computing the transition terms is fixed. Programmability is provided through the selection of the particular programmable state-machine inputs used in the computation. Additionally, each separate reference to a programmable state-machine input in the transition term equations may specify whether the input value or the compliment of the input value is used in the computation. As an example, transition term one could be (Input 1) AND (not Input 2) AND (Input 4); transition term five could be (Input 2) AND (Input 8); and transition term nine could be (not Input 12). The transition terms are computed by the term computation unit 502 within the programmable state-machine 302, 402. The transition term computation unit 502 communicates with the programming register 510 which controls which state-machine inputs are used in the computation of each transition term. The programming register 510 also controls whether the input values or the compliment of the input values are used in each computation (described above). The programming register 510 is written to by at least one initialization task executing on a task engine 120 following system reset. During operation, on each application clock cycle the state controller 504 first updates the current state with the next state computed during the previous clock cycle. The programmable state-machine output signals are updated with the values defined for the new current state. The programmable state-machine 302, 402 then evaluates each of the twelve transition terms as described above. Next, each of the state-transition arcs of the current state are evaluated in order by examining the transition terms associated with each transition arc. The first transition arc encountered which contains a logical true transition term determines the next (new) state. On the next clock cycle, this process repeats. On power up, the programmable state-machine 302, 402 is held in state 0 until a '0' value is written (by an initialization task executing on a task engine 120) to a special 'hold' register within the programmable state-machine 302, 402. This feature allows for predictable programmable state-machine 302, 402 operation while the programming registers 510 that control the programmable state-machine 302, 402 operation are being written to an initialization task executing on a task engine 120.

Both the parallel interface control unit 208 and the serial interface control unit 214 contain a control register 310, 410 and atask register 312, 412. Both the parallel interface control unit C 208 and the serial interface control unit C 214 are connected to a set of control pins 230, 240, a pair of programmable state-machines 302, 402 (within the parallel or serial units) and the two task-engine interface units 222.

The control register 310, 410 is used to communicate control data. This control data can

be external control signals communicated through control pins 230, 240 to or from the interface control unit 208, 214. The control data can also be control signals communicated between the pair of programmable state-machines 302 in the parallel interface units A 204 and B 206 or between the pair of programmable state-machines 402 in the serial interface units A 210 and B 212. The control data can be control signals communicated between the states of a programmable state-machine 302, 402, or control signals to or from a task engine 120 through a task engine interface unit 222.

For each control register control pin 230, 240 in the pin module 104, there is a corresponding bit in the control register 310, 410. In one embodiment, the control register 310, 410 consists of eight bits. Each control register bit can operate in one of several modes. These modes include input control, output control, tri-state output control, and bi-directional control.

The control register bits can be read by the programmable state-machines 302, 402 or a task engine interface unit 222. A control register bit is read by a programmable state-machine 302,

402 if the state-transition term includes the control register bit as one of the programmable state- machine inputs used in the computation of a state-transition term (described above). The mode that each control bit operates in is controlled by a programmable configuration register within each parallel interface control unit C 208 and serial interface control unit C 214. These programmable configuration registers are written to by an initialization task executing on a task engine 120 following system reset. For each control bit that is programmed to be in input control mode, external control data drives the corresponding control pin 230, 240, which, in turn, drives the bit in the control register 310, 410. Additionally, the programmable state-machine outputs that set or clear the control register bit are disabled. Similarly, the ability of a task-engine interface unit 222 to write to this bit is disabled. Each control bit that is programmed to be in output control mode may be set or cleared by one of the programmable state-machines 302, 402 or a task engine 120 through a task engine interface unit 222. The corresponding control pin 230, 240 is then driven with the value of the control register bit.

Each control bit that is programmed to be in tri-state control mode may be set or cleared by one of the programmable state-machines 302, 402 or a task engine 120 (through a task engine interface unit 222). Additionally, the programmable configuration register within the parallel control unit C 208 or the programmable configuration register within the serial control unit C 214 is also used to select an output enable signal for the corresponding control pin 230, 240. The control register bit then drives the corresponding control pin 230, 230 if the selected output enable signal is high. If the selected output enable signal is low, the control pin 230, 240 is not driven (i.e. it is set to a high impedance state). In one embodiment, the output enable signal may be selected from control register bits [0] to [3].

Bi-directional control mode is implemented by combining input control mode with tri- state output control mode. When the output enable signal is high, the programmable state-

machines 302, 402 or a task engine 120 set or clear one or more control register bits. The control register bits in turn drive the corresponding control pins 230, 240. When the output enable signal is low, external control data drive one or more of the control pins 230, 240 which, in turn, drive the corresponding control register bits in the control register 310, 410. The task register 312, 412 is also used to communicate control data. This control data can be control signals communicated between the programmable state-machines 302 in the parallel interface units A 204 and B 206 or between the programmable state-machines 402 in the serial interface units A 210 and B 212, or control signals corresponding to an I/O task being queued to the task queue 220 In one embodiment, the task register 312, 412 consists of four bits. The task register bits can be read by the programmable state-machines 302, 402 if the programming of a state- transition term includes the task register bit as one of the programmable state machine inputs used in the computation of a state-transition term (described above). The programmable state- machine 302, 402 also includes output signals that set and clear the task register bits. The task register bits can also be set by the I/O task queue 220. The I/O task queue 220 monitors the queue bus 124 and performs tasks queued to the I/O module 108 over the queue bus 124. These pre-defined tasks include tasks to set the bits of the task register 312 within the parallel control unit C 208 and the task register 412 within the serial control unit C 214 Fig. 4 is a block diagram illustrative of serial interface unit A 210, serial interface unit B

212, and a serial interface control unit C 214 in the I/O module 108 according to one embodiment of the present invention. Referring to Figs. 2 and 4, the serial interface units A 210 and B 212 are used in the implementation serial data communication. Both serial interface units A 210 and B 212 contain a FIFO queue 406, a thirty-two bit serial buffer 404, a bit match unit

408, a programmable state-machine 402, and a set of serial data pins 236, 244. The FIFO queue

406 is used to buffer data between the data pins 236, 244 and the task engine interface unit 222.

The programmable state-machine 402 (discussed above) is used to implement the control associated with an I/O protocol. The serial buffer 404 is used as an interface between serial data pins 236, 244 and FIFO queue 406.

Serial interface units A 210 and B 212 are connected to a single serial interface control unit C 214. The serial interface control unit C 214 facilitates the communication of control data between the serial interface unit A 210, serial interface unit B 212, a set of control pins 240, a task engine interface unit 222, and the I/O task queue 220. A program executing on a task engine 120 can, through a task engine interface unit 222, write data to or read data from the FIFO queue 406. The transfer of data to/from the task engines 120 is synchronized to the internal system clock signal 252. The programmable state-machine 402 controls the transfer of data to and from the data pins 236, 244, the serial buffer 404, and the FIFO queue 406. These transfers are synchronized to an externally supplied application clock signal 248. Each serial interface unit A 210 and B 212 includes a programmable configuration register which controls the operation of each of the data pins 226,234 and the serial buffer 404. This programmable configuration register is written to by an initialization task executed by a task engine 120 following system reset. In one embodiment, each of the serial interface units A 210 and B 212 are connected to a set of 4 data pins 236, 244 and can be programmed (via the programmable configuration register) for 1, 2, 3 or 4-bit serial operation, hi 1-bit operation, only pin 0 is used. In 2-bit operation, pins 0 and 1 are used. In 3-bit operation, pins 0,1 and 2 are used. In 4-bit operation, all the serial pins are used. Serial data pins 236, 244 can be programmed for input, output, tri-state output, or bi-directional operation. The programmable configuration register is also used to select an output enable signal. If the serial data pins 236,

244 are programmed for tri-state output or bi-directional operation, the output enable signal controls when the pins are driven. If the selected output enable signal is high, the serial data pins

236, 244 are driven with values from the serial buffer 404. If the selected output enable signal is low, the serial data pins 236, 244 are not driven (i.e. they are set to a high impedance state). In one embodiment, the output enable signal may be selected from the control register bits [0] to [3] in the serial interface control unit C 214. The serial data pins 236, 244 are programmed as a group and cannot be directly read from or written to by a task engine 120.

The serial buffer 404 serves as an interface between serial data pins 236, 244 and the FIFO queue 406. The serial buffer 404 can be used as either an input buffer or an output buffer. When the serial buffer 404 is used as an input buffer, serial pin data is sequentially shifted into the serial buffer 404 from the serial data pins 236, 244 and then written to the FIFO queue 406 in thirty-two bit words. When the serial buffer 404 is used as an output buffer, thirty-two bit data is loaded into the serial buffer 404 from the FIFO queue 406 and then sequentially shifted out to the serial data pins 236, 244. The operation of the serial buffer 404 is controlled by the programmable state-machine

402. Control is specified through three control signals which include the FIFO-enable signal, the shift-enable signal, and the I/O-direction signal from the I/O direction unit 508. If the I/O- direction signal is set to input and the shift-enable signal is true, the data in the serial buffer 404 is shifted, otherwise the data is held in the serial buffer 404. If the I/O-direction signal is set to output and a parallel-enable signal is true, the serial buffer 404 is loaded from the FIFO queue

406, otherwise the data is held in the FIFO queue 406. The programmable configuration register within the serial interface control unit C 214 controls the direction (left or right) and number of bits (1,2,3 or 4) for each shift operation.

Data driven onto data pins 236, 244 which are configured for output, tri-state, or bidirectional operation is controlled by a combination of the programmable state-machine outputs and the programmable configuration register. If the data-select output signal of the programmable state-machine 402 is high, then the output data is read from the left or right most bits of the serial buffer 404, depending on the direction (left or right) specified in the programmable configuration register. If the data-select output signal of the state-machine 402 is low, the serial data outputs of the state-machine 402 are used instead of the serial buffer 404. The pattern match unit 408 within a serial interface unit A 210 or B 212 compares two pattern registers (which are within the pattern match unit 408) with the content of the serial buffer 404. The results of these two pattern comparisons are provided as input signals to the programmable state-machine 402. The pattern registers within the pattern match unit 408 are programmable and are written to (through a task engine interface unit 222) by an initialization task executed by a task engine 120 following system reset.

While the invention has been particularly shown and described with reference to specific preferred embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

We claim: 1. An input/output module for use with a plurality of task engines, said input/output module comprising:

a) a plurality of data paths each electrically connected to one or more of a plurality of resources, wherein said plurality of data paths are pre-defined and wherein the data-flow of said plurality of data paths is determined by one of said plurality of task engines under program control; and b) a plurality of control paths each electrically connected to one or more of said plurality of resources, wherein said plurality of control paths are pre-defined and wherein the control-flow of said plurality of control paths is determined by one of said plurality of task engines under program control.

2. The input/output module of claim 1 , wherein the data-flow of said plurality of data paths corresponds to inbound data originating from at least one device external to said input/output module and transmitted to at least one of said plurality of task engines.

3. The input/output module of claim 1 , wherein the data-flow of said plurality of data paths corresponds to outbound data originating from at least one of said plurality of task engines and transmitted to at least one device external to said input/output module.

4. The input/output module of claim 1 , wherein the control-flow of said plurality of control paths corresponds to inbound data originating from at least one device external to said input/output module and transmitted to a control unit internal to said input/output module.

5. The input/output module of claim 1 , wherein the control-flow of said plurality of control paths corresponds to outbound data originating from at least one of said plurality of task engines and transmitted to a control unit internal to said input/output module.

6. The input/output module of claim 1 , further comprising at least one programmable state machine comprising: a plurality of pre-defined input signals; a plurality of pre-defined output signals; and a plurality of programmable states, wherein each programmable state comprises a plurality of programmable state transitions and a plurality of output signal values, wherein said at least one programmable state machine controls the transfer of data and control between said input/output module and an external device.

7. The input/output module of claim 6, wherein said transfer of data and control between said input/output module and said external device conforms to a defined transfer protocol.

8. The input/output module of claim 6, wherein said at least one programmable state machine controls the sequencing of said transfer of data and control between said input/output module and said external device.

9. The input/output module of claim 6, wherein said plurality of programmable state transitions are programmed through a plurality of transition terms.

10. The input/output module of claim 9, wherein each of said plurality of transition terms is computed using a logical combination of at least one of said plurality of pre-defined state machine input signals.

11. The input/output module of claim 10, wherein said logical combination of at least one of said plurality of pre-defined state machine input signals is programmable.

12. The input/output module of claim 1 further comprising a programmable control interface in communication with at least one of said plurality of task engines, said programmable control interface comprising a programmable table, said programming table comprising task queue transactions, wherein said task queue transactions are used with a bus for communication of control with said at least one of said plurality of task engines, wherein said programmable control interface facilitates communication of control between any of said plurality of task engines and said input/output module.

13. The input/output module of claim 1 further comprising a memory mapped data interface in communication with at least one of said plurality of task engines, wherein said memory mapped data interface facilitates data transfers to and from said input/output module.

14. The input/output module of claim 1 further comprising: a) . a control data register, wherein said control data register facilitates communication of control data between said programmable state-machines, said external device, and said plurality of task engines; and

b) a programmable register, wherein said programmable register controls accesses to the control data register.

15. A method of controlling data flow into and out of an input/output module in commimication with one or more external devices, at least one task engine, and a bus, said method comprising: a) loading a program into said at least one task engine; and b) transferring data between said input/output module, said one or more external devices, said at least one task engine, and said data bus in response to said program in said task engine.

16. The method of claim 15 further comprising transferring data between said input/output module, said one or more external devices, said at least one task engine, and said data bus according to a defined data transfer protocol.

17. The method of claim 15, further comprising providing at least one programmable state machine, said at least one programmable state machine being internal to said input/output module, comprising: a plurality of pre-defined input signals; a plurality of pre-defined output signals; and a plurality of programmable states, wherein each of said programmable states comprising a plurality of programmable state transitions and a plurality of output signals, wherein said at least one programmable state machine controls the sequencing of said transfer of data between said input/output module, said one or more external devices, said at least one task engine, and said data bus.

18. The method of claim 15, further comprising transferring data and control between said input/output module, said one or more external devices, said at least one task engine, and said data bus according to a defined data transfer protocol.

19. The method of claim 17, further comprising programming said plurality of programmable state transitions through a plurality of transition terms.

20. The method of claim 19, further comprising computing each of said plurality of transition terms using a logical combination of at least one of said plurality of pre-defined state machine input signals, wherein said logical combination of at least one of said plurality of pre-defined state machine input signals is programmable.

21. An input/output module for use with a plurality of task engines, each of said plurality of task engines in communication with a bus, said input/output module comprising: a) a first input/output port for communication with at least one external device; b) a second input/output port for communication with one of a plurality of task engines; and c) a third input/output port for communication with said bus, wherein a data stream moves between each of said ports under program control by one of said plurality of task engines.

22. The input/output module of claim 21 , wherein a program is stored on one of said plurality of task engines.

23. The input/output module of claim 21 , wherein said second input/output port is in communication with one of a plurality of shared memory modules through one of said plurality of task engines.

24. The input/output module of claim 23 , wherein said one of said plurality of shared memory modules provides a communication path between one of said plurality of task engines and a second of said plurality of task engines.