WO2001071490A3 - A software configurable input/output module - Google Patents

A software configurable input/output module Download PDF

Info

Publication number
WO2001071490A3
WO2001071490A3 PCT/US2001/006307 US0106307W WO0171490A3 WO 2001071490 A3 WO2001071490 A3 WO 2001071490A3 US 0106307 W US0106307 W US 0106307W WO 0171490 A3 WO0171490 A3 WO 0171490A3
Authority
WO
WIPO (PCT)
Prior art keywords
module
configuration registers
resources
output module
configurable input
Prior art date
Application number
PCT/US2001/006307
Other languages
French (fr)
Other versions
WO2001071490A2 (en
Inventor
Oz Levia
Raymond Ryan
Cary Ussery
Original Assignee
Improv Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Improv Systems Inc filed Critical Improv Systems Inc
Priority to AU2001241819A priority Critical patent/AU2001241819A1/en
Publication of WO2001071490A2 publication Critical patent/WO2001071490A2/en
Publication of WO2001071490A3 publication Critical patent/WO2001071490A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention relates to a software configurable input/output module for an Application Specific Integrated Circuit (ASIC). The I/O module serves as a programmable interface between a plurality of task engines and a plurality of external devices and includes a pre-defined set of resources and interconnections between those resources which are used to implement I/O protocols. The I/O module is programmed through a set of internal programmable configuration registers which are written to by one or more initialization tasks executing on a connected task engine. Once these programmable configuration registers are written to, the I/O module responds to data and control signals in a defined manner. The programmable configuration registers enable the selection and combination of these pre-defined resources to implement specific I/O protocols used for the communication of data and control between external devices and task engines.
PCT/US2001/006307 2000-03-23 2001-02-28 A software configurable input/output module WO2001071490A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001241819A AU2001241819A1 (en) 2000-03-23 2001-02-28 A software configurable input/output module

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19140300P 2000-03-23 2000-03-23
US60/191,403 2000-03-23
US62757700A 2000-07-28 2000-07-28
US09/627,577 2000-07-28

Publications (2)

Publication Number Publication Date
WO2001071490A2 WO2001071490A2 (en) 2001-09-27
WO2001071490A3 true WO2001071490A3 (en) 2002-02-21

Family

ID=26887024

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/006307 WO2001071490A2 (en) 2000-03-23 2001-02-28 A software configurable input/output module

Country Status (2)

Country Link
AU (1) AU2001241819A1 (en)
WO (1) WO2001071490A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8930594B1 (en) 2013-08-09 2015-01-06 Google Inc. Integrated circuit with a pinmux crossbar and virtual pins for peripheral connectivity
US11622464B2 (en) 2020-02-24 2023-04-04 Selec Controls Private Limited Modular and configurable electrical device group

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593380A (en) * 1984-06-04 1986-06-03 General Electric Co. Dual function input/output for a programmable controller
US5617559A (en) * 1994-08-31 1997-04-01 Motorola Inc. Modular chip select control circuit and method for performing pipelined memory accesses
WO1999028840A1 (en) * 1997-12-01 1999-06-10 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593380A (en) * 1984-06-04 1986-06-03 General Electric Co. Dual function input/output for a programmable controller
US5617559A (en) * 1994-08-31 1997-04-01 Motorola Inc. Modular chip select control circuit and method for performing pipelined memory accesses
WO1999028840A1 (en) * 1997-12-01 1999-06-10 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture

Also Published As

Publication number Publication date
WO2001071490A2 (en) 2001-09-27
AU2001241819A1 (en) 2001-10-03

Similar Documents

Publication Publication Date Title
US7539848B1 (en) Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor
KR100358631B1 (en) Application specific processor and design method for same
EP1416388A4 (en) Integrated circuit device
US5579531A (en) System for selecting path among plurality of paths using plurality of multiplexers coupled to common bus to transfer data between peripheral devices and external device
WO2005041023A3 (en) System and method using embedded microprocessor as a node in an adaptable computing machine
WO2002077849A3 (en) Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
CA2446983A1 (en) Programmable logic device including programmable interface core and central processing unit
WO2004044674A3 (en) Observation tool for signal processing components
WO2002025957A3 (en) Memory module and memory component built-in self test
WO2003050677A3 (en) System and method for modelling and/or executing software applications, especially mes applications
WO2005073825A3 (en) Protection against power analysis attacks
WO2003054722A3 (en) Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
EP1536332A3 (en) Programmable configuration integrated circuit
US20010044862A1 (en) Serializing and deserialing parallel information for communication between devices for communicating with peripheral buses
CA2461540A1 (en) A reconfigurable integrated circuit with a scalable architecture
EP1754161A1 (en) Digital interface supporting internal and external usb transceivers
WO2001071490A3 (en) A software configurable input/output module
RU2248034C1 (en) Logical converter
US5561773A (en) Programmable, multi-purpose virtual pin multiplier
WO2001014960A3 (en) Generic interface for a software module
WO2003050705A3 (en) Method and system for managing hardware resources to implement system acquisition using an adaptive computing architecture
EP1703637A3 (en) Digital finite impulse response filter
WO2004025700A3 (en) Programmable serial interface for a semiconductor circuit
WO2004029804A3 (en) Real time-capable control system having an sps application under a non-real time-capable operating system
KR100426304B1 (en) Smart card emulator and emulation method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP