DE69431549D1 - Verfahren zur Einebnung von Halbleiterbauflächen und durch dieses Verfahren hergestellte Bauelemente - Google Patents

Verfahren zur Einebnung von Halbleiterbauflächen und durch dieses Verfahren hergestellte Bauelemente

Info

Publication number
DE69431549D1
DE69431549D1 DE69431549T DE69431549T DE69431549D1 DE 69431549 D1 DE69431549 D1 DE 69431549D1 DE 69431549 T DE69431549 T DE 69431549T DE 69431549 T DE69431549 T DE 69431549T DE 69431549 D1 DE69431549 D1 DE 69431549D1
Authority
DE
Germany
Prior art keywords
components produced
semiconductor surfaces
leveling
leveling semiconductor
produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69431549T
Other languages
English (en)
Other versions
DE69431549T2 (de
Inventor
Yoshiyuki Ohkura
Hideki Harada
Tadasi Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69431549D1 publication Critical patent/DE69431549D1/de
Publication of DE69431549T2 publication Critical patent/DE69431549T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/025—Deposition multi-step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69431549T 1993-09-20 1994-07-28 Verfahren zur Einebnung von Halbleiterbauflächen und durch dieses Verfahren hergestellte Bauelemente Expired - Lifetime DE69431549T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23394793 1993-09-20

Publications (2)

Publication Number Publication Date
DE69431549D1 true DE69431549D1 (de) 2002-11-21
DE69431549T2 DE69431549T2 (de) 2003-02-20

Family

ID=16963118

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69431549T Expired - Lifetime DE69431549T2 (de) 1993-09-20 1994-07-28 Verfahren zur Einebnung von Halbleiterbauflächen und durch dieses Verfahren hergestellte Bauelemente

Country Status (3)

Country Link
US (2) US5448111A (de)
EP (1) EP0644590B1 (de)
DE (1) DE69431549T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420095B1 (en) * 1994-03-18 2002-07-16 Fujitsu Limited Manufacture of semiconductor device using A-C anti-reflection coating
EP0820095A3 (de) * 1996-07-19 1999-01-27 Sony Corporation Herstellungsverfahren für eine Zwischenschicht
US6848727B1 (en) * 1999-02-18 2005-02-01 Atoma International Corp Power door latch assembly
US7253104B2 (en) * 2003-12-01 2007-08-07 Micron Technology, Inc. Methods of forming particle-containing materials
JP4509868B2 (ja) * 2005-06-07 2010-07-21 株式会社東芝 半導体装置の製造方法
US7514125B2 (en) * 2006-06-23 2009-04-07 Applied Materials, Inc. Methods to improve the in-film defectivity of PECVD amorphous carbon films
JP5580563B2 (ja) * 2009-09-25 2014-08-27 旭化成イーマテリアルズ株式会社 エアギャップ構造体及びエアギャップ形成方法
US9248176B2 (en) 2010-10-07 2016-02-02 The Texas A&M University System Controlled release vaccines and methods for treating Brucella diseases and disorders
EP3550475A1 (de) 2018-04-06 2019-10-09 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Puf-film und verfahren zur herstellung desselben
EP3550623B1 (de) * 2018-04-06 2020-07-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Puf-film und verfahren zur herstellung davon
EP3550466B1 (de) 2018-04-06 2023-08-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Puf-film und verfahren zur herstellung davon

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US3598761A (en) * 1969-10-06 1971-08-10 Owens Illinois Inc Conductor compositions for microcircuitry
US3660156A (en) * 1970-08-19 1972-05-02 Monsanto Co Semiconductor doping compositions
DE2517743C3 (de) * 1975-04-22 1980-03-06 Jenaer Glaswerk Schott & Gen., 6500 Mainz Passivierender Schutzüberzug für Siliziumhalbleiterbauelemente
JPS54140884A (en) * 1978-04-24 1979-11-01 Nec Corp Manufacture of semiconductor device
JPS5512735A (en) * 1978-07-13 1980-01-29 Sumitomo Electric Ind Ltd Semiconductor device
JPS55117242A (en) * 1979-02-28 1980-09-09 Matsushita Electric Ind Co Ltd Fabrication of semiconductor device
US4222792A (en) * 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
JPS56104443A (en) * 1980-01-23 1981-08-20 Hitachi Ltd Manufacture of semiconductor device
US4544576A (en) * 1981-07-27 1985-10-01 International Business Machines Corporation Deep dielectric isolation by fused glass
JPS60107233A (ja) * 1983-11-14 1985-06-12 Fujitsu Ltd ガス放電パネルの製造方法
US4514580A (en) * 1983-12-02 1985-04-30 Sri International Particulate silicon photovoltaic device and method of making
JPS618941A (ja) * 1984-06-23 1986-01-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPS61212056A (ja) * 1985-03-18 1986-09-20 Toshiba Corp 固体撮像装置
JPH0697660B2 (ja) * 1985-03-23 1994-11-30 日本電信電話株式会社 薄膜形成方法
US4804254A (en) * 1986-01-27 1989-02-14 Autodisplay A/S Arrangement in a display or instrument board
JPS62221137A (ja) * 1986-03-24 1987-09-29 Hitachi Ltd 半導体装置及びその製造方法
JPH084109B2 (ja) * 1987-08-18 1996-01-17 富士通株式会社 半導体装置およびその製造方法
US5078801A (en) * 1990-08-14 1992-01-07 Intel Corporation Post-polish cleaning of oxidized substrates by reverse colloidation
JPH04236435A (ja) * 1991-01-18 1992-08-25 Toshiba Corp 半導体素子の実装方法
JP2538722B2 (ja) * 1991-06-20 1996-10-02 株式会社半導体プロセス研究所 半導体装置の製造方法
DE69230988T2 (de) * 1991-09-23 2000-11-30 Koninklijke Philips Electronics N.V., Eindhoven Verfahren zum Herstellen einer Anordnung, bei dem ein Stoff in einen Körper implantiert wird
JPH05175194A (ja) * 1991-12-20 1993-07-13 Fujitsu Ltd 半導体装置の製造方法
JPH05283542A (ja) * 1992-03-31 1993-10-29 Mitsubishi Electric Corp 半導体集積回路装置及びその製造方法
JP3218515B2 (ja) * 1992-06-16 2001-10-15 富士通株式会社 ポリマー・ブレンド膜の表面平坦化方法
JPH0697298A (ja) * 1992-09-14 1994-04-08 Fujitsu Ltd 半導体装置の絶縁膜の形成方法
US5264395A (en) * 1992-12-16 1993-11-23 International Business Machines Corporation Thin SOI layer for fully depleted field effect transistors
US5258334A (en) * 1993-01-15 1993-11-02 The U.S. Government As Represented By The Director, National Security Agency Process of preventing visual access to a semiconductor device by applying an opaque ceramic coating to integrated circuit devices
US5434451A (en) * 1993-01-19 1995-07-18 International Business Machines Corporation Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines
US5458912A (en) * 1993-03-08 1995-10-17 Dow Corning Corporation Tamper-proof electronic coatings
US5436083A (en) * 1994-04-01 1995-07-25 Dow Corning Corporation Protective electronic coatings using filled polysilazanes
US5436084A (en) * 1994-04-05 1995-07-25 Dow Corning Corporation Electronic coatings using filled borosilazanes

Also Published As

Publication number Publication date
EP0644590A2 (de) 1995-03-22
EP0644590A3 (de) 1996-03-13
DE69431549T2 (de) 2003-02-20
US5448111A (en) 1995-09-05
US5691237A (en) 1997-11-25
EP0644590B1 (de) 2002-10-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE