ATE257611T1 - Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software - Google Patents

Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software

Info

Publication number
ATE257611T1
ATE257611T1 AT96870126T AT96870126T ATE257611T1 AT E257611 T1 ATE257611 T1 AT E257611T1 AT 96870126 T AT96870126 T AT 96870126T AT 96870126 T AT96870126 T AT 96870126T AT E257611 T1 ATE257611 T1 AT E257611T1
Authority
AT
Austria
Prior art keywords
objects
digital system
heterogeneous
ports
primitive
Prior art date
Application number
AT96870126T
Other languages
English (en)
Inventor
Rompaey Karl Van
Diederik Verkest
Jan Vanhoof
Bill Lin
Ivo Bolsens
Man Hugo De
Original Assignee
Imec Inter Uni Micro Electr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/592,697 external-priority patent/US6212566B1/en
Application filed by Imec Inter Uni Micro Electr filed Critical Imec Inter Uni Micro Electr
Application granted granted Critical
Publication of ATE257611T1 publication Critical patent/ATE257611T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/10—Requirements analysis; Specification techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Stored Programmes (AREA)
  • Devices For Executing Special Programs (AREA)
  • Computer And Data Communications (AREA)
  • Circuits Of Receivers In General (AREA)
AT96870126T 1995-10-23 1996-10-03 Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software ATE257611T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US601295P 1995-10-23 1995-10-23
US08/592,697 US6212566B1 (en) 1996-01-26 1996-01-26 Interprocess communication protocol system modem
US1986796P 1996-06-17 1996-06-17

Publications (1)

Publication Number Publication Date
ATE257611T1 true ATE257611T1 (de) 2004-01-15

Family

ID=27358012

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96870126T ATE257611T1 (de) 1995-10-23 1996-10-03 Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software

Country Status (3)

Country Link
EP (1) EP0772140B1 (de)
AT (1) ATE257611T1 (de)
DE (1) DE69631278T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7113901B1 (en) 1997-03-14 2006-09-26 Interuniversitair Microelektronica Centrum (Imec) Reuse of hardware components
US6606588B1 (en) 1997-03-14 2003-08-12 Interuniversitair Micro-Elecktronica Centrum (Imec Vzw) Design apparatus and a method for generating an implementable description of a digital system
US6152612A (en) * 1997-06-09 2000-11-28 Synopsys, Inc. System and method for system level and circuit level modeling and design simulation using C++
US5999734A (en) * 1997-10-21 1999-12-07 Ftl Systems, Inc. Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models
US6321376B1 (en) 1997-10-27 2001-11-20 Ftl Systems, Inc. Apparatus and method for semi-automated generation and application of language conformity tests
US5949993A (en) * 1997-10-31 1999-09-07 Production Languages Corporation Method for the generation of ISA simulators and assemblers from a machine description
GB9723440D0 (en) * 1997-11-06 1998-01-07 Int Computers Ltd Simulation model for a digital system
WO1999030206A1 (fr) 1997-12-05 1999-06-17 Citizen Watch Co., Ltd. Dispositif a cristaux liquides et procede de commande de ce dernier
EP0991000A3 (de) * 1998-09-29 2006-05-17 Interuniversitair Micro-Elektronica Centrum Vzw Wiederverwendung von Hardwarekomponenten
GB9828381D0 (en) * 1998-12-22 1999-02-17 Isis Innovation Hardware/software codesign system
EP1022654A3 (de) * 1999-01-14 2001-02-14 Interuniversitair Microelektronica Centrum Vzw Verfahren und Umgebung für Entwurf von gleichzeitigen,zeitgesteuerten digitalen Systemen
DE19921128A1 (de) * 1999-05-07 2000-11-23 Vrije Universiteit Brussel Bru Verfahren zum Erzeugen von zielsystemspezifischen Programmcodes, Simulationsverfahren sowie Hardwarekonfiguration
GB0001585D0 (en) * 2000-01-24 2000-03-15 Radioscape Ltd Method of designing,modelling or fabricating a communications baseband stack
GB0001577D0 (en) * 2000-01-24 2000-03-15 Radioscape Ltd Software for designing modelling or performing digital signal processing
US7036106B1 (en) 2000-02-17 2006-04-25 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6763327B1 (en) * 2000-02-17 2004-07-13 Tensilica, Inc. Abstraction of configurable processor functionality for operating systems portability
WO2001095161A2 (en) 2000-06-02 2001-12-13 Virtio Corporation Method and system for virtual prototyping
US7069204B1 (en) * 2000-09-28 2006-06-27 Cadence Design System, Inc. Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements
GB2380004A (en) 2001-07-27 2003-03-26 Virtual Access Ireland Ltd A configuration and management development system for a netwok of devices
TW595140B (en) * 2002-04-22 2004-06-21 Cognio Inc System and method for spectrum management of a shared frequency band
AU2003236894A1 (en) * 2002-05-27 2003-12-12 Radioscape Limited A method of designing a system for real time digital signal processing, in which the system uses a virtual machine layer
JP2007526539A (ja) 2003-06-18 2007-09-13 アンブリック， インコーポレイテッド 集積回路開発システム
AT508852B1 (de) * 2009-09-18 2015-11-15 Kompetenzzentrum Das Virtuelle Fahrzeug Forschungsgmbh Vif Verfahren zum umschalten von heterogenen simulationsmodellen zur laufzeit
US9250900B1 (en) 2014-10-01 2016-02-02 Cadence Design Systems, Inc. Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network

Also Published As

Publication number Publication date
DE69631278T2 (de) 2004-11-18
DE69631278D1 (de) 2004-02-12
EP0772140A1 (de) 1997-05-07
EP0772140B1 (de) 2004-01-07

Similar Documents

Publication Publication Date Title
ATE257611T1 (de) Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software
AU2001261386A1 (en) Migrating processes using data representation language representations of the processes in a distributed computing environment
WO1997048033A3 (en) Data representation for mixed-language program development
CA2087735A1 (en) System for high-level virtual computer with heterogeneous operating systems
WO2002025426A3 (en) Lazy compilation of template-generated classes in dynamic compilation execution environments
EP1065611A3 (de) Entwurfssystem zum kombinierten Entwurf von Hardware und Software
Hanson et al. The SL5 procedure mechanism
Savolainen et al. Positioning of modelling approaches, methods and tools
Roberts et al. A perspective on object-oriented simulation
Gadducci et al. Comparing logics for rewriting: Rewriting logic, action calculi and tile logic
Gray et al. Object-based programming in Fortran 90
US7353159B2 (en) Method for parallel simulation on a single microprocessor using meta-models
Peña et al. Deriving Non-Hierarchical Process Topologies.
Brown et al. Software specification and prototyping technologies
KR20200066418A (ko) Llvm 중간언어를 이용한 vr/ar 교육 플랫폼의 딥러닝 적용에 대한 방법 및 시스템
Kummer et al. A framework for interacting design/cpn-and java-processes
Pecevski et al. PCSIM: a parallel simulation environment for neural circuits fully integrated with Python
Mügge et al. Object-Oriented Specification of Models and Experiments in Traffic Simulation
Suslov et al. Simulating heterogeneous models on multi-core platforms using Julia's computing language parallel potential
Kummer et al. Symmetric communication between coloured Petri net simulations and Java-processes
Breitinger et al. Channel Structures in the Parallel Functional Language Eden
Cornelis et al. Neurospaces: Towards automated model partitioning for parallel computers
Deng et al. Fast software prototype development for chassis/driveline controls and integration
Lakhoua et al. Approach of analysis of methods SA, SADT and SART
JPH1173306A (ja) クライアント／サーバ・プログラム生成装置及びクライアント／サーバ・プログラム生成方法

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties