ATE231259T1 - Dynamischer hierarchischer leitwegverzeichnisorganisationsassoziativspeich r - Google Patents

Dynamischer hierarchischer leitwegverzeichnisorganisationsassoziativspeich r

Info

Publication number
ATE231259T1
ATE231259T1 AT91304492T AT91304492T ATE231259T1 AT E231259 T1 ATE231259 T1 AT E231259T1 AT 91304492 T AT91304492 T AT 91304492T AT 91304492 T AT91304492 T AT 91304492T AT E231259 T1 ATE231259 T1 AT E231259T1
Authority
AT
Austria
Prior art keywords
entries
common
value
associative storage
hierarchical routing
Prior art date
Application number
AT91304492T
Other languages
English (en)
Inventor
Steven J Frank
Iii Henry Burkhardt
James B Rothnie
David I Epstein
Stephen W Morss
Dana R Kelly
Paul A Binder
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/526,396 external-priority patent/US5226039A/en
Priority claimed from US07/531,506 external-priority patent/US5341483A/en
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE231259T1 publication Critical patent/ATE231259T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
    • H04L2012/562—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Devices For Executing Special Programs (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AT91304492T 1990-05-18 1991-05-17 Dynamischer hierarchischer leitwegverzeichnisorganisationsassoziativspeich r ATE231259T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/526,396 US5226039A (en) 1987-12-22 1990-05-18 Packet routing switch
US07/531,506 US5341483A (en) 1987-12-22 1990-05-31 Dynamic hierarchial associative memory

Publications (1)

Publication Number Publication Date
ATE231259T1 true ATE231259T1 (de) 2003-02-15

Family

ID=27062104

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91304492T ATE231259T1 (de) 1990-05-18 1991-05-17 Dynamischer hierarchischer leitwegverzeichnisorganisationsassoziativspeich r

Country Status (3)

Country Link
EP (1) EP0458552B1 (de)
AT (1) ATE231259T1 (de)
DE (1) DE69133189T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105450524B (zh) * 2015-12-08 2020-06-09 北京飞讯数码科技有限公司 一种媒体转发路由优化计算的方法
CN117568404B (zh) * 2024-01-16 2024-03-15 四川大学华西医院 多指（趾）相关的基因片段以及动物模型构建方法及应用

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US4811203A (en) * 1982-03-03 1989-03-07 Unisys Corporation Hierarchial memory system with separate criteria for replacement and writeback without replacement
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system

Also Published As

Publication number Publication date
EP0458552B1 (de) 2003-01-15
DE69133189D1 (de) 2003-02-20
EP0458552A3 (en) 1992-08-05
EP0458552A2 (de) 1991-11-27
DE69133189T2 (de) 2003-10-09

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties