ATE203114T1 - Datenstapel und austauschbefehl - Google Patents
Datenstapel und austauschbefehlInfo
- Publication number
- ATE203114T1 ATE203114T1 AT95303669T AT95303669T ATE203114T1 AT E203114 T1 ATE203114 T1 AT E203114T1 AT 95303669 T AT95303669 T AT 95303669T AT 95303669 T AT95303669 T AT 95303669T AT E203114 T1 ATE203114 T1 AT E203114T1
- Authority
- AT
- Austria
- Prior art keywords
- stack
- data stack
- remap array
- processor
- exchange command
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
- G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30112—Register structure comprising data of variable length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Advance Control (AREA)
- Vehicle Body Suspensions (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/252,303 US5696955A (en) | 1994-06-01 | 1994-06-01 | Floating point stack and exchange instruction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE203114T1 true ATE203114T1 (de) | 2001-07-15 |
Family
ID=22955456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT95303669T ATE203114T1 (de) | 1994-06-01 | 1995-05-30 | Datenstapel und austauschbefehl |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5696955A (de) |
| EP (1) | EP0685789B1 (de) |
| JP (1) | JP3714992B2 (de) |
| AT (1) | ATE203114T1 (de) |
| DE (1) | DE69521647T2 (de) |
Families Citing this family (65)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5574670A (en) * | 1994-08-24 | 1996-11-12 | Advanced Micro Devices, Inc. | Apparatus and method for determining a number of digits leading a particular digit |
| BR9509845A (pt) | 1994-12-02 | 1997-12-30 | Intel Corp | Microprocessador com operação de compactação de elementos de operação compósitos |
| US5901302A (en) * | 1995-01-25 | 1999-05-04 | Advanced Micro Devices, Inc. | Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions |
| US6321182B1 (en) * | 1995-03-27 | 2001-11-20 | Canon Kabushiki Kaisha | Method and system for predicting a signal generated in signal processing apparatus |
| WO1997015001A2 (en) * | 1995-10-06 | 1997-04-24 | Patriot Scientific Corporation | Risc microprocessor architecture |
| US5872947A (en) * | 1995-10-24 | 1999-02-16 | Advanced Micro Devices, Inc. | Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions |
| US5892936A (en) * | 1995-10-30 | 1999-04-06 | Advanced Micro Devices, Inc. | Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register |
| US5701508A (en) * | 1995-12-19 | 1997-12-23 | Intel Corporation | Executing different instructions that cause different data type operations to be performed on single logical register file |
| US5857096A (en) * | 1995-12-19 | 1999-01-05 | Intel Corporation | Microarchitecture for implementing an instruction to clear the tags of a stack reference register file |
| US5940859A (en) | 1995-12-19 | 1999-08-17 | Intel Corporation | Emptying packed data state during execution of packed data instructions |
| US6792523B1 (en) | 1995-12-19 | 2004-09-14 | Intel Corporation | Processor with instructions that operate on different data types stored in the same single logical register file |
| US5944818A (en) * | 1996-06-28 | 1999-08-31 | Intel Corporation | Method and apparatus for accelerated instruction restart in a microprocessor |
| US5867680A (en) * | 1996-07-24 | 1999-02-02 | Advanced Micro Devices, Inc. | Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions |
| US6049863A (en) * | 1996-07-24 | 2000-04-11 | Advanced Micro Devices, Inc. | Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor |
| JP2933027B2 (ja) * | 1996-08-30 | 1999-08-09 | 日本電気株式会社 | 複数命令並列発行/実行管理装置 |
| JP2933026B2 (ja) * | 1996-08-30 | 1999-08-09 | 日本電気株式会社 | 複数命令並列発行/実行管理装置 |
| EP0851343B1 (de) * | 1996-12-31 | 2005-08-31 | Metaflow Technologies, Inc. | System zur Ausführung von Gleitkommaoperationen |
| US5930492A (en) * | 1997-03-19 | 1999-07-27 | Advanced Micro Devices, Inc. | Rapid pipeline control using a control word and a steering word |
| US5913048A (en) * | 1997-03-31 | 1999-06-15 | International Business Machines Corporation | Dispatching instructions in a processor supporting out-of-order execution |
| US6088786A (en) * | 1997-06-27 | 2000-07-11 | Sun Microsystems, Inc. | Method and system for coupling a stack based processor to register based functional unit |
| US5948098A (en) * | 1997-06-30 | 1999-09-07 | Sun Microsystems, Inc. | Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines |
| US5961636A (en) * | 1997-09-22 | 1999-10-05 | International Business Machines Corporation | Checkpoint table for selective instruction flushing in a speculative execution unit |
| US5913047A (en) | 1997-10-29 | 1999-06-15 | Advanced Micro Devices, Inc. | Pairing floating point exchange instruction with another floating point instruction to reduce dispatch latency |
| AU745449B2 (en) * | 1997-11-20 | 2002-03-21 | Hajime Seki | Computer system |
| US6112018A (en) * | 1997-12-18 | 2000-08-29 | Advanced Micro Devices, Inc. | Apparatus for exchanging two stack registers |
| US6112296A (en) * | 1997-12-18 | 2000-08-29 | Advanced Micro Devices, Inc. | Floating point stack manipulation using a register map and speculative top of stack values |
| US6018798A (en) * | 1997-12-18 | 2000-01-25 | Advanced Micro Devices, Inc. | Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle |
| US6192461B1 (en) * | 1998-01-30 | 2001-02-20 | International Business Machines Corporation | Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle |
| US6094716A (en) | 1998-07-14 | 2000-07-25 | Advanced Micro Devices, Inc. | Register renaming in which moves are accomplished by swapping rename tags |
| US6151669A (en) * | 1998-10-10 | 2000-11-21 | Institute For The Development Of Emerging Architectures, L.L.C. | Methods and apparatus for efficient control of floating-point status register |
| US6240503B1 (en) * | 1998-11-12 | 2001-05-29 | Advanced Micro Devices, Inc. | Cumulative lookahead to eliminate chained dependencies |
| SE513431C2 (sv) * | 1999-01-11 | 2000-09-11 | Ericsson Telefon Ab L M | Buffert för icke-rapporterade hopp |
| US6327697B1 (en) | 1999-06-28 | 2001-12-04 | Sun Microsystems, Inc. | Method for routing conductive paths in an integrated circuit |
| US6438664B1 (en) | 1999-10-27 | 2002-08-20 | Advanced Micro Devices, Inc. | Microcode patch device and method for patching microcode using match registers and patch routines |
| US6668315B1 (en) * | 1999-11-26 | 2003-12-23 | Hewlett-Packard Development Company, L.P. | Methods and apparatus for exchanging the contents of registers |
| US6757816B1 (en) * | 1999-12-30 | 2004-06-29 | Intel Corporation | Fast branch misprediction recovery method and system |
| US7496734B1 (en) * | 2000-04-28 | 2009-02-24 | Stmicroelectronics, Inc. | System and method for handling register dependency in a stack-based pipelined processor |
| US6725361B1 (en) * | 2000-06-16 | 2004-04-20 | Transmeta Corporation | Method and apparatus for emulating a floating point stack in a translation process |
| US7054898B1 (en) | 2000-08-04 | 2006-05-30 | Sun Microsystems, Inc. | Elimination of end-around-carry critical path in floating point add/subtract execution unit |
| DE10133913A1 (de) * | 2001-07-12 | 2003-01-30 | Infineon Technologies Ag | Programmgesteuerte Einheit |
| US6549442B1 (en) | 2002-07-25 | 2003-04-15 | Neomagic Corp. | Hardware-assisted fast bank-swap in a content-addressable-memory (CAM) processor |
| US6970999B2 (en) * | 2002-07-31 | 2005-11-29 | International Business Machines Corporation | Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters |
| US7043626B1 (en) | 2003-10-01 | 2006-05-09 | Advanced Micro Devices, Inc. | Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming |
| EP1810128B1 (de) * | 2004-08-30 | 2009-11-11 | Texas Instruments Incorporated | Verfahren und vorrichtungen zur zweigvorhersage und verarbeitung von mikroprozessoranweisungen und dergleichen |
| US20070192573A1 (en) * | 2006-02-16 | 2007-08-16 | Guillermo Savransky | Device, system and method of handling FXCH instructions |
| GB2447968B (en) * | 2007-03-30 | 2010-07-07 | Transitive Ltd | Improvements in and relating to floating point operations |
| GB2448370B (en) * | 2007-04-14 | 2012-09-05 | Jds Uniphase Corp | Method of decoding a bit sequence, network element apparatus and PDU specification toolkit |
| US7895422B2 (en) * | 2008-02-29 | 2011-02-22 | Freescale Semiconductor, Inc. | Selective postponement of branch target buffer (BTB) allocation |
| US7937573B2 (en) * | 2008-02-29 | 2011-05-03 | Freescale Semiconductor, Inc. | Metric for selective branch target buffer (BTB) allocation |
| US8495699B2 (en) | 2008-12-23 | 2013-07-23 | At&T Intellectual Property I, L.P. | Distributed content analysis network |
| US20100223660A1 (en) * | 2009-02-27 | 2010-09-02 | At&T Intellectual Property I, L.P. | Providing multimedia content with time limit restrictions |
| US20100223673A1 (en) * | 2009-02-27 | 2010-09-02 | At&T Intellectual Property I, L.P. | Providing multimedia content with access restrictions |
| US8904421B2 (en) * | 2009-06-30 | 2014-12-02 | At&T Intellectual Property I, L.P. | Shared multimedia experience including user input |
| US9330383B1 (en) | 2015-09-23 | 2016-05-03 | Square, Inc. | Message dispatcher for payment system |
| US10248940B1 (en) | 2015-09-24 | 2019-04-02 | Square, Inc. | Modular firmware for transaction system |
| US10108412B2 (en) | 2016-03-30 | 2018-10-23 | Square, Inc. | Blocking and non-blocking firmware update |
| US11010765B2 (en) | 2016-06-29 | 2021-05-18 | Square, Inc. | Preliminary acquisition of payment information |
| US10817869B2 (en) | 2016-06-29 | 2020-10-27 | Square, Inc. | Preliminary enablement of transaction processing circuitry |
| US10417628B2 (en) | 2016-06-29 | 2019-09-17 | Square, Inc. | Multi-interface processing of electronic payment transactions |
| US10761970B2 (en) * | 2017-10-20 | 2020-09-01 | International Business Machines Corporation | Computerized method and systems for performing deferred safety check operations |
| US10762196B2 (en) | 2018-12-21 | 2020-09-01 | Square, Inc. | Point of sale (POS) systems and methods with dynamic kernel selection |
| US11049095B2 (en) | 2018-12-21 | 2021-06-29 | Square, Inc. | Point of sale (POS) systems and methods with dynamic kernel selection |
| US10990969B2 (en) | 2018-12-21 | 2021-04-27 | Square, Inc. | Point of sale (POS) systems and methods for dynamically processing payment data based on payment reader capability |
| CN114691209B (zh) * | 2020-12-30 | 2025-07-22 | 龙芯中科技术股份有限公司 | 浮点栈处理方法、装置及处理器 |
| CN118152007B (zh) * | 2024-05-10 | 2024-07-19 | 深圳市华普微电子股份有限公司 | 一种最小栈的硬件实现方法 |
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| US5367650A (en) * | 1992-07-31 | 1994-11-22 | Intel Corporation | Method and apparauts for parallel exchange operation in a pipelined processor |
| IE80854B1 (en) * | 1993-08-26 | 1999-04-07 | Intel Corp | Processor ordering consistency for a processor performing out-of-order instruction execution |
| US5499352A (en) * | 1993-09-30 | 1996-03-12 | Intel Corporation | Floating point register alias table FXCH and retirement floating point register array |
-
1994
- 1994-06-01 US US08/252,303 patent/US5696955A/en not_active Expired - Lifetime
-
1995
- 1995-05-30 AT AT95303669T patent/ATE203114T1/de not_active IP Right Cessation
- 1995-05-30 DE DE69521647T patent/DE69521647T2/de not_active Expired - Lifetime
- 1995-05-30 EP EP95303669A patent/EP0685789B1/de not_active Expired - Lifetime
- 1995-05-31 JP JP13401295A patent/JP3714992B2/ja not_active Expired - Fee Related
-
1997
- 1997-11-12 US US08/967,950 patent/US5857089A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5696955A (en) | 1997-12-09 |
| JPH07334362A (ja) | 1995-12-22 |
| JP3714992B2 (ja) | 2005-11-09 |
| EP0685789A3 (de) | 1996-12-04 |
| DE69521647D1 (de) | 2001-08-16 |
| EP0685789A2 (de) | 1995-12-06 |
| DE69521647T2 (de) | 2002-05-29 |
| US5857089A (en) | 1999-01-05 |
| EP0685789B1 (de) | 2001-07-11 |
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| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |