DE69734093D1 - System zur Ausführung von Gleitkommaoperationen - Google Patents

System zur Ausführung von Gleitkommaoperationen

Info

Publication number
DE69734093D1
DE69734093D1 DE69734093T DE69734093T DE69734093D1 DE 69734093 D1 DE69734093 D1 DE 69734093D1 DE 69734093 T DE69734093 T DE 69734093T DE 69734093 T DE69734093 T DE 69734093T DE 69734093 D1 DE69734093 D1 DE 69734093D1
Authority
DE
Germany
Prior art keywords
point operations
executing floating
floating
executing
operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69734093T
Other languages
English (en)
Inventor
David L Isaman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Metaflow Technologies Inc
Original Assignee
Metaflow Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Metaflow Technologies Inc filed Critical Metaflow Technologies Inc
Application granted granted Critical
Publication of DE69734093D1 publication Critical patent/DE69734093D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
DE69734093T 1996-12-31 1997-12-12 System zur Ausführung von Gleitkommaoperationen Expired - Lifetime DE69734093D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US77558396A 1996-12-31 1996-12-31

Publications (1)

Publication Number Publication Date
DE69734093D1 true DE69734093D1 (de) 2005-10-06

Family

ID=25104852

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69734093T Expired - Lifetime DE69734093D1 (de) 1996-12-31 1997-12-12 System zur Ausführung von Gleitkommaoperationen

Country Status (4)

Country Link
US (1) US6035391A (de)
EP (1) EP0851343B1 (de)
JP (1) JP3841131B2 (de)
DE (1) DE69734093D1 (de)

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US6112018A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Apparatus for exchanging two stack registers
US6094716A (en) * 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
US6230262B1 (en) 1998-07-31 2001-05-08 Advanced Micro Devices, Inc. Processor configured to selectively free physical registers upon retirement of instructions
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6240503B1 (en) 1998-11-12 2001-05-29 Advanced Micro Devices, Inc. Cumulative lookahead to eliminate chained dependencies
US6523106B1 (en) * 1998-12-21 2003-02-18 Intel Corporation Method and apparatus for efficient pipelining
US6338134B1 (en) 1998-12-29 2002-01-08 International Business Machines Corporation Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data
US6564312B1 (en) * 1999-06-15 2003-05-13 Koninklijke Philips Electronics N.V. Data processor comprising an arithmetic logic unit
US6339823B1 (en) * 1999-07-20 2002-01-15 Ip-First, L.L.C. Method and apparatus for selective writing of incoherent MMX registers
US6581155B1 (en) * 1999-08-25 2003-06-17 National Semiconductor Corporation Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same
US6343296B1 (en) * 1999-09-03 2002-01-29 Lucent Technologies Inc. On-line reorganization in object-oriented databases
US6584907B2 (en) * 2000-03-17 2003-07-01 Ensign-Bickford Aerospace & Defense Company Ordnance firing system
US7496734B1 (en) * 2000-04-28 2009-02-24 Stmicroelectronics, Inc. System and method for handling register dependency in a stack-based pipelined processor
WO2002069224A1 (en) 2001-02-21 2002-09-06 United States Postal Service Systems and methods for utilizing a tracking label in an item delivery system
WO2002069180A1 (en) * 2001-02-21 2002-09-06 United States Postal Service Systems and methods for processing items in an item delivery system
WO2002069245A1 (en) * 2001-02-21 2002-09-06 United States Postal Service Improved tracking label
US7143937B2 (en) * 2001-02-21 2006-12-05 United States Postal Service Systems and methods for utilizing a tracking label in an item delivery system
US6895498B2 (en) * 2001-05-04 2005-05-17 Ip-First, Llc Apparatus and method for target address replacement in speculative branch target address cache
US7165169B2 (en) * 2001-05-04 2007-01-16 Ip-First, Llc Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
US7134005B2 (en) * 2001-05-04 2006-11-07 Ip-First, Llc Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
US7165168B2 (en) * 2003-01-14 2007-01-16 Ip-First, Llc Microprocessor with branch target address cache update queue
US20020194461A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Speculative branch target address cache
US7707397B2 (en) * 2001-05-04 2010-04-27 Via Technologies, Inc. Variable group associativity branch target address cache delivering multiple target addresses per cache line
US7200740B2 (en) * 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
US6886093B2 (en) * 2001-05-04 2005-04-26 Ip-First, Llc Speculative hybrid branch direction predictor
US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US7203824B2 (en) * 2001-07-03 2007-04-10 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US6823444B1 (en) * 2001-07-03 2004-11-23 Ip-First, Llc Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
US7234045B2 (en) * 2001-07-03 2007-06-19 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7159097B2 (en) * 2002-04-26 2007-01-02 Ip-First, Llc Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
US7210026B2 (en) 2002-06-28 2007-04-24 Sun Microsystems, Inc. Virtual register set expanding processor internal storage
US7203820B2 (en) * 2002-06-28 2007-04-10 Sun Microsystems, Inc. Extending a register file utilizing stack and queue techniques
US7152154B2 (en) * 2003-01-16 2006-12-19 Ip-First, Llc. Apparatus and method for invalidation of redundant branch target address cache entries
US7143269B2 (en) * 2003-01-14 2006-11-28 Ip-First, Llc Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
US7185186B2 (en) * 2003-01-14 2007-02-27 Ip-First, Llc Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
US7178010B2 (en) * 2003-01-16 2007-02-13 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
US7237098B2 (en) * 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US7043626B1 (en) 2003-10-01 2006-05-09 Advanced Micro Devices, Inc. Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
US20070192573A1 (en) * 2006-02-16 2007-08-16 Guillermo Savransky Device, system and method of handling FXCH instructions
US9201656B2 (en) 2011-12-02 2015-12-01 Arm Limited Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers
US8914616B2 (en) * 2011-12-02 2014-12-16 Arm Limited Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed
US10417001B2 (en) * 2012-12-27 2019-09-17 Intel Corporation Physical register table for eliminating move instructions
MA44821A (fr) * 2016-02-27 2019-01-02 Kinzinger Automation Gmbh Procédé d'allocation d'une pile de registres virtuels dans une machine à pile

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US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
GB9112754D0 (en) * 1991-06-13 1991-07-31 Int Computers Ltd Data processing apparatus
US5522051A (en) * 1992-07-29 1996-05-28 Intel Corporation Method and apparatus for stack manipulation in a pipelined processor
US5367650A (en) * 1992-07-31 1994-11-22 Intel Corporation Method and apparauts for parallel exchange operation in a pipelined processor
US5551004A (en) * 1993-05-28 1996-08-27 Sgs-Thomson Microelectronics, Inc. Structure which renders faulty data of a cache memory uncacheable in order that a partially functional cache memory may be utilized
US5499352A (en) * 1993-09-30 1996-03-12 Intel Corporation Floating point register alias table FXCH and retirement floating point register array
US5613132A (en) * 1993-09-30 1997-03-18 Intel Corporation Integer and floating point register alias table within processor device
US5548776A (en) * 1993-09-30 1996-08-20 Intel Corporation N-wide bypass for data dependencies within register alias table
US5826094A (en) * 1993-09-30 1998-10-20 Intel Corporation Register alias table update to indicate architecturally visible state
US5696955A (en) * 1994-06-01 1997-12-09 Advanced Micro Devices, Inc. Floating point stack and exchange instruction
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
US5634118A (en) * 1995-04-10 1997-05-27 Exponential Technology, Inc. Splitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translation

Also Published As

Publication number Publication date
JP3841131B2 (ja) 2006-11-01
EP0851343A2 (de) 1998-07-01
EP0851343B1 (de) 2005-08-31
US6035391A (en) 2000-03-07
EP0851343A3 (de) 2000-03-22
JPH10254699A (ja) 1998-09-25

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