DE69739384D1 - Multiprozessorsystem ausgestaltet zur Ausführung von softwareinitiierten Vorausladeoperationen - Google Patents

Multiprozessorsystem ausgestaltet zur Ausführung von softwareinitiierten Vorausladeoperationen

Info

Publication number
DE69739384D1
DE69739384D1 DE69739384T DE69739384T DE69739384D1 DE 69739384 D1 DE69739384 D1 DE 69739384D1 DE 69739384 T DE69739384 T DE 69739384T DE 69739384 T DE69739384 T DE 69739384T DE 69739384 D1 DE69739384 D1 DE 69739384D1
Authority
DE
Germany
Prior art keywords
system configured
multiprocessor system
perform software
prefetch operations
initiated prefetch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69739384T
Other languages
English (en)
Inventor
Erik E Hagersten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69739384D1 publication Critical patent/DE69739384D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
DE69739384T 1996-07-01 1997-06-27 Multiprozessorsystem ausgestaltet zur Ausführung von softwareinitiierten Vorausladeoperationen Expired - Fee Related DE69739384D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/674,273 US5848254A (en) 1996-07-01 1996-07-01 Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space

Publications (1)

Publication Number Publication Date
DE69739384D1 true DE69739384D1 (de) 2009-06-10

Family

ID=24705988

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69739384T Expired - Fee Related DE69739384D1 (de) 1996-07-01 1997-06-27 Multiprozessorsystem ausgestaltet zur Ausführung von softwareinitiierten Vorausladeoperationen

Country Status (4)

Country Link
US (1) US5848254A (de)
EP (1) EP0818733B1 (de)
JP (1) JPH10143476A (de)
DE (1) DE69739384D1 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249520B1 (en) * 1997-10-24 2001-06-19 Compaq Computer Corporation High-performance non-blocking switch with multiple channel ordering constraints
US6578110B1 (en) 1999-01-21 2003-06-10 Sony Computer Entertainment, Inc. High-speed processor system and cache memories with processing capabilities
US6282626B1 (en) * 1999-07-15 2001-08-28 3Com Corporation No stall read access-method for hiding latency in processor memory accesses
US6408363B1 (en) * 2000-05-04 2002-06-18 Hewlett-Packard Company Speculative pre-flush of data in an out-of-order execution processor system
US6826619B1 (en) 2000-08-21 2004-11-30 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6487643B1 (en) 2000-09-29 2002-11-26 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6772298B2 (en) 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US6791412B2 (en) 2000-12-28 2004-09-14 Intel Corporation Differential amplifier output stage
US7234029B2 (en) 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US6721918B2 (en) 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US6971098B2 (en) 2001-06-27 2005-11-29 Intel Corporation Method and apparatus for managing transaction requests in a multi-node architecture
US6934809B2 (en) * 2002-02-22 2005-08-23 Sun Microsystems, Inc. Automatic prefetch of pointers
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7321956B2 (en) * 2004-03-25 2008-01-22 International Business Machines Corporation Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches
US7363432B2 (en) * 2004-03-25 2008-04-22 International Business Machines Corporation Method and apparatus for directory-based coherence with distributed directory management
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8493397B1 (en) * 2004-11-15 2013-07-23 Nvidia Corporation State machine control for a pipelined L2 cache to implement memory transfers for a video processor
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US8683126B2 (en) * 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US20090106498A1 (en) * 2007-10-23 2009-04-23 Kevin Michael Lepak Coherent dram prefetcher
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8780123B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8681861B2 (en) * 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) * 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8200905B2 (en) 2008-08-14 2012-06-12 International Business Machines Corporation Effective prefetching with multiple processors and threads
US8489851B2 (en) * 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
US8667225B2 (en) * 2009-09-11 2014-03-04 Advanced Micro Devices, Inc. Store aware prefetching for a datastream
US8892822B2 (en) * 2011-11-29 2014-11-18 Oracle International Corporation Selectively dropping prefetch requests based on prefetch accuracy information
WO2016023166A1 (zh) * 2014-08-12 2016-02-18 华为技术有限公司 管理文件的方法、分布式存储系统和管理节点
EP3835959A4 (de) * 2018-08-24 2021-11-10 Huawei Technologies Co., Ltd. Verfahren und vorrichtung zum daten-prefetching

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
US5524225A (en) * 1992-12-18 1996-06-04 Advanced Micro Devices Inc. Cache system and method for providing software controlled writeback

Also Published As

Publication number Publication date
EP0818733A3 (de) 1998-08-19
EP0818733A2 (de) 1998-01-14
EP0818733B1 (de) 2009-04-29
JPH10143476A (ja) 1998-05-29
US5848254A (en) 1998-12-08

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee