ATE180907T1 - Arithmetik-logik-einheit - Google Patents

Arithmetik-logik-einheit

Info

Publication number
ATE180907T1
ATE180907T1 AT92308109T AT92308109T ATE180907T1 AT E180907 T1 ATE180907 T1 AT E180907T1 AT 92308109 T AT92308109 T AT 92308109T AT 92308109 T AT92308109 T AT 92308109T AT E180907 T1 ATE180907 T1 AT E180907T1
Authority
AT
Austria
Prior art keywords
output
coupled
logic unit
arithmetic logic
bus
Prior art date
Application number
AT92308109T
Other languages
English (en)
Inventor
Michael A Nix
John G Bartkowiak
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE180907T1 publication Critical patent/ATE180907T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Hardware Redundancy (AREA)
  • Advance Control (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
AT92308109T 1991-10-29 1992-09-08 Arithmetik-logik-einheit ATE180907T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US78383891A 1991-10-29 1991-10-29

Publications (1)

Publication Number Publication Date
ATE180907T1 true ATE180907T1 (de) 1999-06-15

Family

ID=25130548

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92308109T ATE180907T1 (de) 1991-10-29 1992-09-08 Arithmetik-logik-einheit

Country Status (5)

Country Link
US (1) US5282153A (de)
EP (1) EP0540150B1 (de)
JP (1) JP3549549B2 (de)
AT (1) ATE180907T1 (de)
DE (1) DE69229324T2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638859B1 (de) * 1993-08-09 1999-09-29 Siemens Aktiengesellschaft Signalverarbeitungseinrichtung
US5436860A (en) * 1994-05-26 1995-07-25 Motorola, Inc. Combined multiplier/shifter and method therefor
GB2300054A (en) * 1995-01-17 1996-10-23 Hewlett Packard Co Clipping integers
US5682339A (en) * 1995-05-26 1997-10-28 National Semiconductor Corporation Method for performing rotate through carry using a 32 bit barrel shifter and counter
DE19632036A1 (de) * 1996-08-08 1998-02-12 Bosch Gmbh Robert Verfahren und Aufbereitung von Abtastwerten
US5844827A (en) * 1996-10-17 1998-12-01 Samsung Electronics Co., Ltd. Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N
US5745393A (en) * 1996-10-17 1998-04-28 Samsung Electronics Company, Ltd. Left-shifting an integer operand and providing a clamped integer result
US5930159A (en) * 1996-10-17 1999-07-27 Samsung Electronics Co., Ltd Right-shifting an integer operand and rounding a fractional intermediate result to obtain a rounded integer result
US6330631B1 (en) * 1999-02-03 2001-12-11 Sun Microsystems, Inc. Data alignment between buses
JP2001308921A (ja) * 2000-04-25 2001-11-02 Sony Corp デマルチプレクサ
KR100457040B1 (ko) * 2000-06-21 2004-11-10 패러데이 테크놀로지 코퍼레이션 곱셈 누산 명령을 이용한 데이터 처리 장치 및 방법
GB2367650B (en) * 2000-10-04 2004-10-27 Advanced Risc Mach Ltd Single instruction multiple data processing
US6975679B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US20030005269A1 (en) * 2001-06-01 2003-01-02 Conner Joshua M. Multi-precision barrel shifting
US6934728B2 (en) * 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US6937084B2 (en) * 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US7020788B2 (en) * 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US7007172B2 (en) * 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6952711B2 (en) * 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US20020184566A1 (en) * 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US20030005268A1 (en) * 2001-06-01 2003-01-02 Catherwood Michael I. Find first bit value instruction
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6985986B2 (en) * 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US20030023836A1 (en) * 2001-06-01 2003-01-30 Michael Catherwood Shadow register array control instructions
US7467178B2 (en) * 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US20030028696A1 (en) * 2001-06-01 2003-02-06 Michael Catherwood Low overhead interrupt
US6976158B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
CN100356314C (zh) * 2003-01-06 2007-12-19 上海奇码数字信息有限公司 可控制锁存累加器的系统与方法
US11973519B2 (en) * 2020-06-23 2024-04-30 Intel Corporation Normalized probability determination for character encoding

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4785393A (en) * 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip
EP0173383B1 (de) * 1984-08-14 1990-04-18 Telecommunications Radioelectriques Et Telephoniques T.R.T. Prozessor zur Verarbeitung von Daten verschiedener Darstellungsarten und geeignetes Multipliziergerät für einen solchen Prozessor
US4682302A (en) * 1984-12-14 1987-07-21 Motorola, Inc. Logarithmic arithmetic logic unit
JPH0644225B2 (ja) * 1986-03-27 1994-06-08 日本電気株式会社 浮動小数点丸め正規化回路
US4760544A (en) * 1986-06-20 1988-07-26 Plessey Overseas Limited Arithmetic logic and shift device
JP2600293B2 (ja) * 1988-06-10 1997-04-16 日本電気株式会社 オーバーフロー補正回路
US5053631A (en) * 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit

Also Published As

Publication number Publication date
JP3549549B2 (ja) 2004-08-04
EP0540150A2 (de) 1993-05-05
JPH05216917A (ja) 1993-08-27
US5282153A (en) 1994-01-25
DE69229324T2 (de) 2000-02-24
DE69229324D1 (de) 1999-07-08
EP0540150B1 (de) 1999-06-02
EP0540150A3 (en) 1994-11-23

Similar Documents

Publication Publication Date Title
DE69229324D1 (de) Arithmetik-Logik-Einheit
ATE185204T1 (de) Signalverarbeitungseinrichtung
DE69416283D1 (de) Überlaufsteuerung für arithmetische Operationen
GB2314649A (en) Exponentiation Circuit Utilizing Shift Means and Method of Using Same
GB2291515B (en) Data processing using multiply-accumulate instructions
ATE291256T1 (de) Acht-bit-mikrokontroller mit risc-architektur
KR910003486A (ko) 비트 순서 전환 장치
CA2325091A1 (en) Bus switch and bus switch system
KR970705074A (ko) "캐리를 통한 순환" 동작 실행 방법(Method for Performing a "Rotate Through Carry" Operation
US4592008A (en) Overflow detector for algebraic adders
JPS6457822A (en) Semiconductor integrated circuit
EP0085762A3 (de) Logische Paritätsschaltung
DE69525209D1 (de) Dynamischer, binärer Hochgeschwindigkeits-Inkrementierer
KR970705071A (ko) 부호달린 나눗셈을 이행하는 방법(Method for Performing Signed Division)
TW431067B (en) Single source differential circuit
EP0108664A3 (de) Mikroprozessor für Gleitkommazahlen
SU1667056A1 (ru) Устройство дл суммировани -вычитани чисел с плавающей зап той
RU2006915C1 (ru) Устройство для сложения
SU1290300A1 (ru) Устройство дл суммировани двух чисел с плавающей зап той
KR970007614A (ko) 곱셈 및 나눗셈 연산용 지원회로
JPS6439169A (en) Run length detecting circuit
SU1019441A1 (ru) Двоично-дес тичный сумматор
KR950022131A (ko) 연산장치
GB2307573A (en) Digital arithmetic circuit
KR970002653A (ko) 랜덤 억세서블 fifo

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties