ATE179263T1 - 7-zu-3-zählerschaltung - Google Patents

7-zu-3-zählerschaltung

Info

Publication number
ATE179263T1
ATE179263T1 AT92304018T AT92304018T ATE179263T1 AT E179263 T1 ATE179263 T1 AT E179263T1 AT 92304018 T AT92304018 T AT 92304018T AT 92304018 T AT92304018 T AT 92304018T AT E179263 T1 ATE179263 T1 AT E179263T1
Authority
AT
Austria
Prior art keywords
carry
bit
inputs
weight
provides
Prior art date
Application number
AT92304018T
Other languages
English (en)
Inventor
Vijay Parmar
Mayur Mehta
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE179263T1 publication Critical patent/ATE179263T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Complex Calculations (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Logic Circuits (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Analogue/Digital Conversion (AREA)
AT92304018T 1991-05-17 1992-05-05 7-zu-3-zählerschaltung ATE179263T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/702,594 US5148388A (en) 1991-05-17 1991-05-17 7 to 3 counter circuit

Publications (1)

Publication Number Publication Date
ATE179263T1 true ATE179263T1 (de) 1999-05-15

Family

ID=24821860

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92304018T ATE179263T1 (de) 1991-05-17 1992-05-05 7-zu-3-zählerschaltung

Country Status (6)

Country Link
US (1) US5148388A (de)
EP (1) EP0514061B1 (de)
JP (1) JPH05197527A (de)
AT (1) ATE179263T1 (de)
DE (1) DE69228961T2 (de)
ES (1) ES2130156T3 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2071556B1 (es) * 1992-12-31 1996-01-16 Alcatel Standard Electrica Dispositivo de reduccion del numero de palabras de datos en operaciones aritmeticas binarias.
US6125379A (en) * 1998-02-11 2000-09-26 The Research Foundation Of State University Of New York Parallel VLSI shift switch logic devices
DE10130484B4 (de) * 2001-03-01 2005-08-18 Infineon Technologies Ag 7-zu-3 Bit Carry-Save Addierer und Addierer damit
EP1643356B1 (de) * 2003-05-23 2010-01-06 Nippon Telegraph and Telephone Corporation Parallelverarbeitungseinrichtung und parallelverarbeitungsverfahren
DE10347077B4 (de) * 2003-10-10 2012-11-29 Infineon Technologies Ag Multibit-Bit-Addierer

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3535502A (en) * 1967-11-15 1970-10-20 Ibm Multiple input binary adder
US3636334A (en) * 1969-01-02 1972-01-18 Univ California Parallel adder with distributed control to add a plurality of binary numbers
US3603776A (en) * 1969-01-15 1971-09-07 Ibm Binary batch adder utilizing threshold counters
FR2101005B1 (de) * 1970-08-05 1976-07-09 Lekarski Simeon
US3711692A (en) * 1971-03-15 1973-01-16 Goodyear Aerospace Corp Determination of number of ones in a data field by addition
US3723715A (en) * 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions
DE2634194A1 (de) * 1976-07-29 1978-02-02 Siemens Ag Mit verknuepfungsgliedern aufgebauter statischer binaercodierer mit mehreren signaleingaengen und mehreren signalausgaengen
US4399517A (en) * 1981-03-19 1983-08-16 Texas Instruments Incorporated Multiple-input binary adder
FR2505581A1 (fr) * 1981-05-08 1982-11-12 Labo Cent Telecommunicat Compteur parallele et application a la realisation d'un additionneur binaire
US4604723A (en) * 1983-10-17 1986-08-05 Sanders Associates, Inc. Bit-slice adder circuit

Also Published As

Publication number Publication date
DE69228961T2 (de) 1999-12-09
EP0514061A3 (en) 1993-05-12
JPH05197527A (ja) 1993-08-06
US5148388A (en) 1992-09-15
ES2130156T3 (es) 1999-07-01
EP0514061A2 (de) 1992-11-19
DE69228961D1 (de) 1999-05-27
EP0514061B1 (de) 1999-04-21

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Legal Events

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