ATE133276T1 - Prozessor zur behandlung von ausnahmebedingungen - Google Patents

Prozessor zur behandlung von ausnahmebedingungen

Info

Publication number
ATE133276T1
ATE133276T1 AT91301103T AT91301103T ATE133276T1 AT E133276 T1 ATE133276 T1 AT E133276T1 AT 91301103 T AT91301103 T AT 91301103T AT 91301103 T AT91301103 T AT 91301103T AT E133276 T1 ATE133276 T1 AT E133276T1
Authority
AT
Austria
Prior art keywords
exception
registers
processes
processor
level
Prior art date
Application number
AT91301103T
Other languages
English (en)
Inventor
William Michael Johnson
Michael D Goddard
Tim Olson
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE133276T1 publication Critical patent/ATE133276T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)
AT91301103T 1990-03-21 1991-02-12 Prozessor zur behandlung von ausnahmebedingungen ATE133276T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/496,762 US5237700A (en) 1990-03-21 1990-03-21 Exception handling processor for handling first and second level exceptions with reduced exception latency

Publications (1)

Publication Number Publication Date
ATE133276T1 true ATE133276T1 (de) 1996-02-15

Family

ID=23974024

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91301103T ATE133276T1 (de) 1990-03-21 1991-02-12 Prozessor zur behandlung von ausnahmebedingungen

Country Status (5)

Country Link
US (1) US5237700A (de)
EP (1) EP0448212B1 (de)
JP (1) JP2951738B2 (de)
AT (1) ATE133276T1 (de)
DE (1) DE69116402T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3590075B2 (ja) * 1992-01-20 2004-11-17 株式会社東芝 仮想記憶方式のデータ処理装置及び方法
US5491793A (en) * 1992-07-31 1996-02-13 Fujitsu Limited Debug support in a processor chip
JPH06180653A (ja) * 1992-10-02 1994-06-28 Hudson Soft Co Ltd 割り込み処理方法および装置
US5386563A (en) * 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
CA2128393C (en) * 1992-12-23 2001-10-02 Jean-Felix Perotto Multi-tasking low-power controller
US5761407A (en) * 1993-03-15 1998-06-02 International Business Machines Corporation Message based exception handler
DE69429061T2 (de) * 1993-10-29 2002-07-18 Advanced Micro Devices Inc Superskalarmikroprozessoren
US5574928A (en) * 1993-10-29 1996-11-12 Advanced Micro Devices, Inc. Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
US5922070A (en) * 1994-01-11 1999-07-13 Texas Instruments Incorporated Pipelined data processing including program counter recycling
US5689693A (en) * 1994-04-26 1997-11-18 Advanced Micro Devices, Inc. Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead
US5696955A (en) * 1994-06-01 1997-12-09 Advanced Micro Devices, Inc. Floating point stack and exchange instruction
EP0685794A1 (de) * 1994-06-01 1995-12-06 Advanced Micro Devices, Inc. System zum Erzeugen von Fliesskomma-Prüfvektoren
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus
WO1996025705A1 (en) * 1995-02-14 1996-08-22 Fujitsu Limited Structure and method for high-performance speculative execution processor providing special features
US5778211A (en) * 1996-02-15 1998-07-07 Sun Microsystems, Inc. Emulating a delayed exception on a digital computer having a corresponding precise exception mechanism
US5729729A (en) * 1996-06-17 1998-03-17 Sun Microsystems, Inc. System for fast trap generation by creation of possible trap masks from early trap indicators and selecting one mask using late trap indicators
US6173248B1 (en) * 1998-02-09 2001-01-09 Hewlett-Packard Company Method and apparatus for handling masked exceptions in an instruction interpreter
US6216222B1 (en) * 1998-05-14 2001-04-10 Arm Limited Handling exceptions in a pipelined data processing apparatus
US6189093B1 (en) * 1998-07-21 2001-02-13 Lsi Logic Corporation System for initiating exception routine in response to memory access exception by storing exception information and exception bit within architectured register
US6289445B2 (en) 1998-07-21 2001-09-11 Lsi Logic Corporation Circuit and method for initiating exception routines using implicit exception checking
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
US6829719B2 (en) * 2001-03-30 2004-12-07 Transmeta Corporation Method and apparatus for handling nested faults
US6981264B1 (en) * 2002-01-17 2005-12-27 Unisys Corporation Method for handling multiple program exceptions across heterogeneous systems
JP4447471B2 (ja) * 2002-11-18 2010-04-07 エイアールエム リミテッド 安全処理システムにおける例外タイプ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50117336A (de) * 1973-11-30 1975-09-13
US4631659A (en) * 1984-03-08 1986-12-23 Texas Instruments Incorporated Memory interface with automatic delay state
US4809157A (en) * 1985-09-30 1989-02-28 International Business Machines Corp. Dynamic assignment of affinity for vector tasks
US4992934A (en) * 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
JPH0682320B2 (ja) * 1988-06-08 1994-10-19 日本電気株式会社 データ処理装置

Also Published As

Publication number Publication date
DE69116402D1 (de) 1996-02-29
JP2951738B2 (ja) 1999-09-20
US5237700A (en) 1993-08-17
EP0448212A3 (en) 1992-08-26
DE69116402T2 (de) 1996-08-01
JPH04223532A (ja) 1992-08-13
EP0448212B1 (de) 1996-01-17
EP0448212A2 (de) 1991-09-25

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee