ATE110903T1 - Interface-schaltung zwischen der ''oder- verdrahteten'' verbindung einer pla-einrichtung und einem ttl-ausgangspuffer. - Google Patents

Interface-schaltung zwischen der ''oder- verdrahteten'' verbindung einer pla-einrichtung und einem ttl-ausgangspuffer.

Info

Publication number
ATE110903T1
ATE110903T1 AT88305296T AT88305296T ATE110903T1 AT E110903 T1 ATE110903 T1 AT E110903T1 AT 88305296 T AT88305296 T AT 88305296T AT 88305296 T AT88305296 T AT 88305296T AT E110903 T1 ATE110903 T1 AT E110903T1
Authority
AT
Austria
Prior art keywords
output buffer
connection
interface circuit
bandgap
circuit
Prior art date
Application number
AT88305296T
Other languages
English (en)
Inventor
Nader Vasseghi
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE110903T1 publication Critical patent/ATE110903T1/de

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00376Modifications for compensating variations of temperature, supply voltage or other physical parameters in bipolar transistor circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)
  • Communication Control (AREA)
AT88305296T 1987-06-25 1988-06-10 Interface-schaltung zwischen der ''oder- verdrahteten'' verbindung einer pla-einrichtung und einem ttl-ausgangspuffer. ATE110903T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/066,915 US4789797A (en) 1987-06-25 1987-06-25 Temperature-compensated interface circuit between "OR-tied" connection of a PLA device and a TTL output buffer

Publications (1)

Publication Number Publication Date
ATE110903T1 true ATE110903T1 (de) 1994-09-15

Family

ID=22072539

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88305296T ATE110903T1 (de) 1987-06-25 1988-06-10 Interface-schaltung zwischen der ''oder- verdrahteten'' verbindung einer pla-einrichtung und einem ttl-ausgangspuffer.

Country Status (5)

Country Link
US (1) US4789797A (de)
EP (1) EP0296739B1 (de)
JP (1) JP2619692B2 (de)
AT (1) ATE110903T1 (de)
DE (1) DE3851272T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444395A (en) * 1993-12-06 1995-08-22 Motorola, Inc. Non-saturating bipolar transistor circuit
US5510733A (en) * 1994-12-23 1996-04-23 Sun Microsystems, Inc. High speed circuit with CMOS and bipolar logic stages
US5712590A (en) * 1995-12-21 1998-01-27 Dries; Michael F. Temperature stabilized bandgap voltage reference circuit
JP5290794B2 (ja) * 2009-02-05 2013-09-18 日本電信電話株式会社 論理回路および論理集積回路
TWI514106B (zh) * 2014-03-11 2015-12-21 Midastek Microelectronic Inc 參考電源產生電路及應用其之電子電路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460865A (en) * 1981-02-20 1984-07-17 Motorola, Inc. Variable temperature coefficient level shifting circuit and method
US4514650A (en) * 1982-10-25 1985-04-30 Burroughs Corporation Low power small area PLA
US4590418A (en) * 1984-11-05 1986-05-20 General Motors Corporation Circuit for generating a temperature stabilized reference voltage
US4626770A (en) * 1985-07-31 1986-12-02 Motorola, Inc. NPN band gap voltage reference
US4677369A (en) * 1985-09-19 1987-06-30 Precision Monolithics, Inc. CMOS temperature insensitive voltage reference
US4701636A (en) * 1986-05-29 1987-10-20 National Semiconductor Corporation Programming voltage control circuit for programmable array logic device
US4677368A (en) * 1986-10-06 1987-06-30 Motorola, Inc. Precision thermal current source

Also Published As

Publication number Publication date
JP2619692B2 (ja) 1997-06-11
EP0296739B1 (de) 1994-08-31
JPS6432530A (en) 1989-02-02
DE3851272D1 (de) 1994-10-06
US4789797A (en) 1988-12-06
DE3851272T2 (de) 1995-03-09
EP0296739A2 (de) 1988-12-28
EP0296739A3 (de) 1991-04-03

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties