ATE101934T1 - Mehrfachport-speichernetzwerk. - Google Patents

Mehrfachport-speichernetzwerk.

Info

Publication number
ATE101934T1
ATE101934T1 AT87304170T AT87304170T ATE101934T1 AT E101934 T1 ATE101934 T1 AT E101934T1 AT 87304170 T AT87304170 T AT 87304170T AT 87304170 T AT87304170 T AT 87304170T AT E101934 T1 ATE101934 T1 AT E101934T1
Authority
AT
Austria
Prior art keywords
signal
providing
transition
binary address
address signals
Prior art date
Application number
AT87304170T
Other languages
English (en)
Inventor
Kent D Lewallen
Moon-Seng Kok
Steve Schumann
Woei-Jian Liu
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE101934T1 publication Critical patent/ATE101934T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Communication Control (AREA)
  • Dram (AREA)
AT87304170T 1986-05-19 1987-05-11 Mehrfachport-speichernetzwerk. ATE101934T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/864,690 US4742493A (en) 1986-05-19 1986-05-19 Multiple port memory array device including improved timing and associated method
EP87304170A EP0250081B1 (de) 1986-05-19 1987-05-11 Mehrfachport-Speichernetzwerk

Publications (1)

Publication Number Publication Date
ATE101934T1 true ATE101934T1 (de) 1994-03-15

Family

ID=25343846

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87304170T ATE101934T1 (de) 1986-05-19 1987-05-11 Mehrfachport-speichernetzwerk.

Country Status (5)

Country Link
US (1) US4742493A (de)
EP (1) EP0250081B1 (de)
JP (1) JP2612446B2 (de)
AT (1) ATE101934T1 (de)
DE (1) DE3789125T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63898A (ja) * 1986-06-19 1988-01-05 Fujitsu Ltd 半導体記憶装置
US5150328A (en) * 1988-10-25 1992-09-22 Internation Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5166903A (en) * 1988-10-25 1992-11-24 International Business Machines Corporation Memory organization with arrays having an alternate data port facility
US4918664A (en) * 1989-01-18 1990-04-17 Cypress Semiconductor Apparatus and method for preserving data integrity in multiple-port RAMS
US5062081A (en) * 1989-10-10 1991-10-29 Advanced Micro Devices, Inc. Multiport memory collision/detection circuitry
FR2672140B1 (fr) * 1991-01-28 1996-08-30 Bosch Gmbh Robert Systeme a multicalculateur.
DE10215362A1 (de) * 2002-04-08 2003-10-30 Infineon Technologies Ag Integrierter Speicher mit einem Speicherzellenfeld mit mehreren Speicherbänken und Schaltungsanordnung mit einem integrierten Speicher
US7888962B1 (en) 2004-07-07 2011-02-15 Cypress Semiconductor Corporation Impedance matching circuit
KR100640876B1 (ko) * 2004-11-17 2006-11-02 엘지전자 주식회사 이동 방송 수신기의 비디오 디코딩 시스템
US8036846B1 (en) 2005-10-20 2011-10-11 Cypress Semiconductor Corporation Variable impedance sense architecture and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4065809A (en) * 1976-05-27 1977-12-27 Tokyo Shibaura Electric Co., Ltd. Multi-processing system for controlling microcomputers and memories
GB2123189B (en) * 1982-06-05 1987-06-10 British Aerospace Communication between computers
US4580245A (en) * 1983-07-28 1986-04-01 Sperry Corporation Complementary metal oxide semiconductor dual port random access memory cell
US4627030A (en) * 1985-02-04 1986-12-02 At&T Bell Laboratories Dual port memory word size expansion technique
US4636991A (en) * 1985-08-16 1987-01-13 Motorola, Inc. Summation of address transition signals

Also Published As

Publication number Publication date
DE3789125D1 (de) 1994-03-31
DE3789125T2 (de) 1994-08-18
JP2612446B2 (ja) 1997-05-21
EP0250081B1 (de) 1994-02-23
EP0250081A2 (de) 1987-12-23
EP0250081A3 (en) 1990-11-07
JPS62298087A (ja) 1987-12-25
US4742493A (en) 1988-05-03

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Legal Events

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