AT516576A3 - Verfahren zum Verbinden von zwei Substraten - Google Patents

Verfahren zum Verbinden von zwei Substraten

Info

Publication number
AT516576A3
AT516576A3 ATA51014/2015A AT510142015A AT516576A3 AT 516576 A3 AT516576 A3 AT 516576A3 AT 510142015 A AT510142015 A AT 510142015A AT 516576 A3 AT516576 A3 AT 516576A3
Authority
AT
Austria
Prior art keywords
substrates
joining
atmosphere
dew point
unit
Prior art date
Application number
ATA51014/2015A
Other languages
English (en)
Other versions
AT516576B1 (de
AT516576A2 (de
Original Assignee
Soitec Silicon On Insulator
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Commissariat Energie Atomique filed Critical Soitec Silicon On Insulator
Publication of AT516576A2 publication Critical patent/AT516576A2/de
Publication of AT516576A3 publication Critical patent/AT516576A3/de
Application granted granted Critical
Publication of AT516576B1 publication Critical patent/AT516576B1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/0007—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding involving treatment or provisions in order to avoid deformation or air inclusion, e.g. to improve surface quality
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/0036—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/0036—Heat treatment
    • B32B2038/0048—Annealing, relaxing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00—Layers arrangement
    • B32B2250/02—2 layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/70—Other properties
    • B32B2307/728—Hydrophilic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/60—In a particular environment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2313/00—Elements other than metals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/14—Semiconductor wafers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D2207/00—Indexing scheme relating to details of indicating measuring values
    • G01D2207/10—Displays which are primarily used in aircraft or display aircraft-specific information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Quality & Reliability (AREA)
  • Thermal Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Analytical Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Ceramic Products (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Combinations Of Printed Boards (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Zum Verbinden von zwei Substraten (1, 2) durch molekulare Adhäsion werden diese in einem ersten Schritt (1) in Kontakt miteinander gebracht, um eine Einheit (3) mit einer Verbindungs-Schnittstelle (4)zu bilden, und in einem zweiten Schritt (b) wird die Adhäsion der Einheit (3) auf über einen Schwellenwert verstärkt, über dem Wasser nicht mehr über die Verbindungs-Schnittstelle diffundieren kann; in einem Schritt (c) der wasserlosen Behandlung werden die Substrate (1, 2) in einer Atmosphäre mit einer Taupunkttemperatur von unter -10°C; und der Kontrolle des Taupunkts der Atmosphäre behandelt, der die Substrate (1, 2) ab diesem Schritt (c) der wasserlosen Behandlung bis zum Ende des zweiten Schritts ausgesetzt sind, um das Auftreten von Klebefehlern an der Verbindungs- Schnittstelle zu begrenzen oder zu verhindern.
AT510142015A 2014-11-27 2015-11-27 Verfahren zum Verbinden von zwei Substraten AT516576B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1461544A FR3029352B1 (fr) 2014-11-27 2014-11-27 Procede d'assemblage de deux substrats

Publications (3)

Publication Number Publication Date
AT516576A2 AT516576A2 (de) 2016-06-15
AT516576A3 true AT516576A3 (de) 2017-11-15
AT516576B1 AT516576B1 (de) 2019-11-15

Family

ID=53298424

Family Applications (1)

Application Number Title Priority Date Filing Date
AT510142015A AT516576B1 (de) 2014-11-27 2015-11-27 Verfahren zum Verbinden von zwei Substraten

Country Status (7)

Country Link
US (1) US9718261B2 (de)
JP (1) JP6643873B2 (de)
KR (1) KR102446438B1 (de)
CN (1) CN105655243B (de)
AT (1) AT516576B1 (de)
DE (1) DE102015223347A1 (de)
FR (1) FR3029352B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA3004245C (en) 2015-11-19 2022-03-15 Blanctec Co., Ltd. Ice, refrigerant, ice production method, method for producing cooled article, method for producing refrigerated article of plant/animal or portion thereof, refrigerating material for plant/animal or portion thereof, method for producing frozen fresh plant/animal or portion thereof, defrosted article or processed article thereof, and freezing material for ...
CA3063833A1 (en) 2017-05-18 2019-12-09 Blanctec Co., Ltd. State change control device and state change control method
CN111640814B (zh) * 2020-06-05 2022-05-20 天津三安光电有限公司 一种太阳电池结构及其制备方法
US12040513B2 (en) 2022-11-18 2024-07-16 Carbon Ventures, Llc Enhancing efficiencies of oxy-combustion power cycles

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080014712A1 (en) * 2006-07-11 2008-01-17 Konstantin Bourdelle Method for direct bonding two semiconductor substrates
US20080014714A1 (en) * 2006-07-11 2008-01-17 Konstantin Bourdelle Method of fabricating a hybrid substrate
EP2200077A1 (de) * 2008-12-22 2010-06-23 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Bindung zweier Substrate
EP2579303A1 (de) * 2011-10-03 2013-04-10 Soitec Verfahren zur Herstellung einer Silizium-auf-Isolator-Struktur
US20140295642A1 (en) * 2011-10-04 2014-10-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Double layer transfer method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193203A (ja) * 1993-12-27 1995-07-28 Canon Inc 半導体基体の製造方法
WO1999010927A1 (en) * 1997-08-29 1999-03-04 Farrens Sharon N In situ plasma wafer bonding method
EP2091071B1 (de) 2008-02-15 2012-12-12 Soitec Verfahren zum Bonden zweier Substrate
US10825793B2 (en) * 2011-04-08 2020-11-03 Ev Group E. Thallner Gmbh Method for permanently bonding wafers
FR2990054B1 (fr) 2012-04-27 2014-05-02 Commissariat Energie Atomique Procede de collage dans une atmosphere de gaz presentant un coefficient de joule-thomson negatif.
US8796054B2 (en) * 2012-05-31 2014-08-05 Corning Incorporated Gallium nitride to silicon direct wafer bonding
FR3000092B1 (fr) * 2012-12-26 2015-01-16 Commissariat Energie Atomique Traitement de surface par plasma chlore dans un procede de collage

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080014712A1 (en) * 2006-07-11 2008-01-17 Konstantin Bourdelle Method for direct bonding two semiconductor substrates
US20080014714A1 (en) * 2006-07-11 2008-01-17 Konstantin Bourdelle Method of fabricating a hybrid substrate
EP2200077A1 (de) * 2008-12-22 2010-06-23 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Bindung zweier Substrate
EP2579303A1 (de) * 2011-10-03 2013-04-10 Soitec Verfahren zur Herstellung einer Silizium-auf-Isolator-Struktur
US20140295642A1 (en) * 2011-10-04 2014-10-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Double layer transfer method

Also Published As

Publication number Publication date
FR3029352B1 (fr) 2017-01-06
US9718261B2 (en) 2017-08-01
US20160152017A1 (en) 2016-06-02
CN105655243A (zh) 2016-06-08
DE102015223347A1 (de) 2016-06-02
KR102446438B1 (ko) 2022-09-22
AT516576B1 (de) 2019-11-15
CN105655243B (zh) 2020-05-15
JP2016103637A (ja) 2016-06-02
AT516576A2 (de) 2016-06-15
JP6643873B2 (ja) 2020-02-12
KR20160064011A (ko) 2016-06-07
FR3029352A1 (fr) 2016-06-03

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