SU1179349A1 - Device for checking microprograms - Google Patents

Abstract

A MICROPROGRAM CONTROL DEVICE containing an address decoder, a pulse counter, a memory block and an AND element, the address input of the device connected to an address decoder input, characterized in that, in order to increase the control reliability, a shift register, a multiplexer and the first and the second triggers, and the input of the attribute of the device operation, the start input and the data input of the device are connected respectively to the information input of the first trigger, the synchronization input of the shift register and the information input The second trigger, the output of which is connected to the data input of the memory block, the device clock input is connected to the first input of the And element and the synchronization input of the second trigger; the first, second, third and fourth outputs of the address decoder are connected respectively to the multiplexer operation input input, the address of the multiplexer , the input of the initial settings of the pulse counter and the synchronization input of the first trigger, the output of which is connected to the zero input of the shift register, the first and second outputs of which are connected according to But with the zero input of the first trigger and the second input of the element I, the fifth output of the address decoder is connected to the read input of the memory block and the subtract input of the pulse counter whose output is connected (L to the first data input of the multiplexer and the address input of the memory block whose output is connected with the second data input of the multiplexer, the output of which is the information output of the device, the output of the AND element is connected to the recording input of the memory unit and the addition input of the pulse counter. her

Description

The invention relates to computing and can be used to automatically control digital devices at the microinstruction level in real time.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 is a block diagram of the device; in fig. 2 - timing charts of the device.

The device address input 1 is connected to the address 2 of the address decoder 3, the input 4 of the sign of the device operation permission, the start input 5 and the device data input 6 are connected respectively to the information input 7 of the first trigger 8, the input 9 of the shift register 10 and the information input 11 of the second trigger 12 whose output 13 is connected to the data input 14 of the memory block 15, the clock input 16 of the device is connected to the first input 17 of the element AND 18 and the synchronization input 19 of the second trigger 12, the first 20, the second 21, the third 22 and the fourth 23 decoder outputs 3 ad The resors are connected respectively to the operation enable input 24 and the address input 26 of the multiplexer 25, the input 27 of the initial settings of the pulse counter 28 and the synchronization input 29 of the first trigger 8, the output 30 of which is connected to the input 31 of the offset register 10, the first 32 and second 33 outputs of which are connected respectively, with the zero input 34 of the first trigger 8 and the second input 35 of the element 18, the fifth output 36 of the address decoder 3 is connected to the read input 37 of the memory block 15 and the subtract input 38 of the pulse counter 28, the output 39 of which is connected to the first input 4 0 data of the multiplexer 25 and the address input 41 of the memory block 15, the output 42 of which is connected to the second data input 43 of the multiplexer 25, the output 44 of which is the information output of the device, the output 45 of the And 18 element is connected to the write input 46 of the memory 15 and the input 47 counters add 28 pulses.

The device works as follows.

A device for controlling firmware is connected to a computer as an external device with the help of a universal communication highway. In the trunk line set, there are an address bus and a data bus. The central processor sets the corresponding address of the device on the bus of the address of the communication highway and communicates with it via the data bus.

The device can operate in the sequential storing mode of information received at the input 6 of the device data and in the mode of issuing the accumulated information to the information output 44.

In the initial state, the first trigger 8 is in the state "O. In this case

the shift is reset and at its outputs 33 and 32, respectively, the states are "O and" 1.

To start the device at the input 4 of the permission of operation, the state "1" is formed, at the same time the address activating the fourth 23 and third 22 outputs of the decoder 3 address is formed at the address input 1 of the device. In this case, the first trigger 8 is set to the state "1, and the pulse counter 28 is reset to" O. Upon arrival at the synchronization input 9 of the shift register of the device start pulse, the state "1" is set at its output 33, and the element 18 is also unlocked, which simultaneously performs the function of a delay line. When forming on the clock input 16 of the device of the rising edge of the pulse, the information prepared at the data input 6 of the device is recorded in the second trigger 12

and from its output is fed to the input 14 of the data of the memory block. After a time interval determined by the delay created by the element I 18, at its output 45, as well as at the input 46 of the recording of the memory unit and at the input 47 of the counter of pulses,

The delayed clock pulse, with the information prepared for this moment at input 14, is recorded in a memory cell, the address of which is given by a code set at address input 41 by pulse counter 28, after which the current value of the counter is increased by one. The process of storing information arriving at the device data input occurs until a stop pulse is generated at the device start input, while

, at the output 32 of the shift register, an “O” is formed, which sets the first trigger and the shift register to zero states, which causes blocking element AND 18. To fetch the accumulated information from the memory block, the address of the device receives the address, which, after decryption, activates the first 20 and fifth 36 outputs of the decoder 3. In this case, the memory block is opened for outputting information from the cell to output 42, whose address is specified by the state of output 39 of the pulse counter.

 At the same time, multiplexer 25 opens to transmit information from its second input 43 to output 44. After removing the device access, the outputs 36 and 20 of the address decoder return to their original

Q state. At the same time, the outputs of memory block 15 and multiplexer 25 are locked, and the pulse counter decreases its value by one, thereby preparing the address of the next in order cell of the memory block from which information will be selected

5 the next access to the device. Sequential reading of information from the cells of the memory block is done to those

until the pulse counter 28 returns to its original (zero) state.

The monitoring of the current state of the pulse counter 28 is carried out by accessing it at the corresponding address set at the address input 1 of the device. This activates

The first 20 and second 21 outputs of the address decimator that configure multiplexer 25 to skip the counter status information from the first input 40 of the multiplexer to its output 44. After removing the call to the pulse counter, the outputs of the address decipher are reset and the output of the multiplexer locked up.

thirty

32

33

pp

sixteen

five

J5

Claims (1)

A DEVICE FOR MONITORING MICROPROGRAMS containing an address decoder, a pulse counter, a memory unit and an AND element, the device address input connected to the address of the address decoder, characterized in that, in order to increase the reliability of the control, a shift register, a multiplexer, and the first and second triggers, and the input sign of the permission of the device, the start input and the data input of the device are connected respectively to the information input of the first trigger, the synchronization input of the shift register and the information input of the second of the trigger, the output of which is connected to the data input of the memory unit, the device’s clock input is connected to the first input of the AND element and the synchronization input of the second trigger, the first, second, third and fourth outputs of the address decoder are connected respectively to the enable input of the multiplexer, the address input of the multiplexer, the input initial settings of the pulse counter and the synchronization input of the first trigger, the output of which is connected to the zero input of the shift register, the first and second outputs of which are connected respectively to the zero the input of the first trigger and the second input of the element And, the fifth output of the address decoder is connected to the read input of the memory block and the input of the subtraction of the pulse counter, the output of which is connected to the first data input of the multiplexer and the address input of the memory block, the output of which is connected to the second data input of the multiplexer, the output of which is the information output of the device, the output of the AND element is connected to the recording input of the memory unit and the input of the addition of the pulse counter.