SU1117627A1 - Interface for linking computer with communication channels - Google Patents

Abstract

A DEVICE FOR PAIRING ELECTRONIC COMPUTING MACHINE WITH COMMUNICATION CHANNELS, containing a clock pulse generator, an information switch group of information inputs of which is a group of information inputs of a device, and a group of address inputs through an address decoder group of the corresponding inputs of the address counter and the first inputs of corresponding elements AND the first group, the outputs of which are connected to the information input of the address memory, the element I, the trigger, the zero input connected to the zero output distribute Comparison, the first input of which is connected to the output of the counter of the number of recorded addresses, characterized in that, in order to increase the reliability of information transfer, the second group of AND elements, the address switch, the OR element and the number of read addresses are entered into it pulses are connected to the clock inputs of the address counter and the distributor, the blocking input of which is connected to the trigger output, the address of the address switch and the address memory mode setting, the output group is a device information output group, the address synchronization memory input is connected to the output of the OR element, and the address input is connected to the output of the address switch, the first information input of which is connected to the output of the counter of the number of written addresses, and the second information input - from the output of the counter the number of read addresses and the second information input of the comparison circuit, the code of which is the device ready output, the first, second and third outputs of the distributor are connected respectively to the first input of the distributor cient OR clock input of the counter recorded addresses and first inputs of the second group of AND gates, the first inputs of which are connected to a group of outputs decrypted torus addresses, and outputs group is a reset device channel outputs blocking input of the counter; addresses are connected to the second inputs: sd of the AND elements of the first group, a single trigger input and an output of the AND element, the first and second inputs of which are connected respectively to the output of the information switch and the input of the device operation mode, the second input of the OR element and the clock input of the number counter The read addresses are connected to the synchronization input D1 and the read operation of the device.

Description

The invention relates to computing and data transmission and can be used in multiplexers and data transfer hubs from communication channels in a computer in order to test the readiness of serial-parallel converters, as well as sensors of discrete information of automatic copying systems. A device for interfacing is known, comprising a switch, a memory unit, the first inputs of which are connected to a counter, a block of elements I, a pulse distributor and a comparison unit, the first input of which is connected to the output of the memory block, the second inputs to the first inputs of a pulse distributor, the third input is with the input of the device and the input of the pulse distributor, the output is with the first input of the I block, the second input of which is connected to the output of the switch, the third input is with the first input of the pulse distributor, the output is with the second input of the switch the memory, the third inputs of which are connected to the second outputs of the pulse distributor, the third output of which is connected to the input of the counter, the outputs of which are connected to the corresponding switch inputs, the fourth input of the memory unit is connected to a quarter output of the distribution of the bodies of pulses, .ij. The drawbacks of the device are high hardware costs and low speed, which is expressed in the necessity of polling each switching element several times, after which the comparator generates a clock signal arriving at the output of the device. In addition, the composition of the equipment is due to the presence of two storage devices. The closest in technical essence to the present invention is a device for interfacing discrete sensors, which contains a switch, the information inputs of which are the corresponding inputs of the device, and the ajgpecHbie inputs are connected to the corresponding outputs of the address decoder, the inputs of which are connected to the corresponding, outputs of the address counter and the first the inputs of the corresponding elements And the group of outputs connected to the corresponding inputs of the current address counter. the output group of which is connected to the register input group and the first input circuit of the comparison circuit, the second input group of which is connected to the register output group, and the output to the control node input, connected to the address counter and register, respectively, to the address memory and encoder , the group of memory addresses of the addresses is connected to the outputs of the corresponding elements AND of the group, the input to the third output of the control node, and the output through the encoder to the output of the device, the switch output is connected to the second input E AND elements and a second group of inputs of the control unit, the group of inputs of which is connected to vkodam.schetchika address. The control node contains the first and second decoders, a trigger, a reversible counter, a generator, the first, second, third and fourth elements AND, the first input of the reversible counter being connected to the second input of the node, the outputs through the first decoder are connected to a single trigger input, and the second reversing input counter. connected to the third code of the control unit and to the output of the first element I, the first input of which is connected to the zero B code of the trigger, and the second input to the generator output, the first input of the second element And and the first input of the third element And the output of the second decoder, whose inputs are a group of inputs of the node, the zero input of the trigger is connected to the first input of the node and the second input of the fourth element And whose output is connected to the third input of the reversible counter, the single input of the trigger is connected to the second input of the second element And, you the stroke of which is the second output of node 2j. The disadvantages of the known device are low reliability of information transfer, since the hard cycle of interrogating the sensors - transferring their state to the computer necessitates the mandatory transfer to the computer of the entire memory contents after the last sensor is polled and the possibility of information loss if the computer is busy processing other information as well as device complexity. The purpose of the invention is to show the reliability of information transfer.

This goal is achieved by the fact that a device for interfacing an electronic computer with communication channels, which contains a clock generator, an information switch, a group of information inputs of which is a group of information inputs of the device, and a group of address inputs through an address decoder are connected to an output group account the address and the first inputs of the corresponding AND elements of the first group, the outputs of which are connected to the information input of the address memory, the AND element, a trigger, a zero input subconnect The zero to the zero output of the distributor, and the comparison circuit, the first input of which is connected to the output of the counter of the number of written addresses, the second group of elements AND, the address switch, the OR element and the counter of the number of read addresses, the output of the clock generator connected to the clock inputs: address counter and the distributor whose blocking input is connected to the trigger output, to the control input of the address switch and to the address setting of the address memory mode, the code group of which is the information output group of the device TWA, the address synchronization memory input is connected to the output of the OR element, and the address input is connected to the output of the address switch, the first information input of which is connected to the output of the counter of the number of written addresses, and the second information input of the counter of the number of read addresses and the second information input comparison circuits whose output is the readiness output of the device, the first, second and third outputs of the distributor are connected respectively to the first input of the OR element, the clock input of the counter of the number / recorded address and the first inputs of elements AND of the second group, the first inputs of which are connected to the output group of the address decoder, and the output group is a group of device channel reset outputs, the blocking input of the address counter is connected to the second inputs of the AND elements of the first group, the single trigger input and the output of the AND element , the first and second inputs of which are connected respectively to the output of the information switch and to the input of the device operation mode the second input of the OR element and the clock input of the counter of the number of counted addresses are connected to the input Om synchronization operation reading device.

The drawing is a functional diagram of the device.

The scheme contains information switch 1, address decoder 2, address 3 counter, clock pulse generator A, element 5, trigger 6, distributor 7, elements 8 and 9 of the second and first groups, counter 10, the number of addresses written, counter 1 the number of read addresses , address switch 12, comparison circuit 13, element OR 14, memory of 15 addresses, group of device 16 information inputs, device read synchronization input 17, device mode input 18, device channel reset outputs group 19, device information output group 20, and output 21 device.

The device works as follows.

After powering the computer, the command causes the reset of all peripheral devices. According to this command, the counters 10 and 11 are reset to O, the bus 18 sets the signal of logical O. Trigger 6 is reset due to the signal of the return connection of the distributor 7 to the pulses from generator 4 switch counter 3, since the signal at its blocking input is O, and do not shift the distributor 7 due to its blocking by the signal from the output of the trigger 6. The trigger 6 prepares the switch 12 to pass the signals, the counter 11 and the memory 15 to the Read operation. At the output of the comparison circuit 13, there is no signal.

After the installation command is given in the initial state, the computer sets 1 at input 18. In this case, the device is brought to a working state — the waiting mode for external information. In the absence of information, the state of the circuit does not change, at the output of the element AND 5 there is no signal, the pulses of the generator 4 are interrogated through the counter 3 and the decoder 2.

When a signal appears at any input of the switch 1, a single signal appears at the output of element 5 and stops counting 3, flips trigger 6 and serves elements 9, through which the code of the polled channel is fed to the information inputs of memory 15. This trigger 6 switches switch 12 to pass signals from counter U, prepares memory 15 for Record and operation. permits the passage of clock pulses to the distributor 7; The signal from the first output of the distributor 7 through the element OR 14 is recorded in memory 15 of the number of the channel polled by the switch 1 in the cell with the address 0 ... 0. The signal from the second output of the distributor 7 transmits into the counter 10 the number O ... 01, preparing for recording a cell with the address 0 ... 01 of memory 15. The signal from the third output of the distributor 7 resets the polled channel to O via one of the open elements And 8 and the signal from the zero output resets the trigger 6 to the initial state, and brings the device into the mode of waiting for information. Since the counter 10 was set to the state 0 ... 01, and the counter 11 remained in the state 0 ... 00, then at the output of the comparison circuit 13 there will be the state 1, which informs the computer about the presence of the recorded information. If the processor of the computer is engaged in the development of a higher priority program, and at the input of the switch 1 there is an information server. it is similarly recorded in memory cells 15. With this 74 counter 10 readings are more and more different from read counter 11, i.e. the counter 10, as it were, runs away from the counter 11. The logic of reading information from the memory of 15 addresses is as follows. The computer removes the resolution from the input 18, while the output of the element And 5 is always O regardless of the availability of information at the inputs of the switch 1. To eliminate information loss, if the removal of the signal at input 18 occurs at the moment (the distributor 7 data recording pulses, the computer makes the address of the device address at input 17 the leading edge of the pulse, through the JPI 14 element reads the cell of memory 15 with the address 0 ... 0, and with the falling edge writes the number 11 ... 01 into the counter 11, i.e. counter 11 as if catches counter 10, information is read until O state at the output of the comparison circuit 13, or before accessing the processor with a higher priority device, i.e., the device does not require full reading of memory 15. After the computer has finished reading, it stops 1 at input 18 and puts the device in the information recording mode. Thus, a device with simpler means provides an increase in the reliability of information flow by eliminating information loss.

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Claims (1)

A device for interfacing an electronic computing machine with communication channels, comprising a clock pulse generator, an information switch, a group of information inputs of which is a group of information inputs of the device, and a group of address inputs through an address decoder is connected to the group of outputs of the address counter and the first inputs of the corresponding elements of the first group, the outputs of which are connected to the information input of the address memory, the AND element, a trigger connected to the zero output of the distributor by a zero input, and comparison, the first input of which is connected to the output of the counter of the number of recorded addresses, characterized in that, in order to increase the reliability of information transfer, a second group of AND elements, an address switch, an OR element and a counter of the number of read addresses are introduced into it, and the output of the clock connected to the clock inputs of the address counter and distributor, the lock input is the counter home of the number of recorded addresses, and the second information input is the counter output of the number of read addresses and the second information input comparisons, the output of which is the device ready output, the first, second and third outputs of the distributor are connected respectively to the first input of the OR element, the clock input of the counter of the number of recorded addresses and the first inputs of the elements of the second group, the first inputs of which are connected to the group of outputs of the address decoder, and the group of outputs is the group of outputs for resetting the channels of the device, the input ^ blocking the counter 'addresses is connected to the second inputs of the AND elements of the first group, a single trigger input and the output of the AND element, the first and second inputs of which are connected respectively to the output of the information switch and · the input of the device operation mode, the second input of the OR element and the clock input of the counter of the number of read addresses are connected to the synchronization input of the device read operation.