SU1142822A1 - Timer - Google Patents

Abstract

1. TIMER containing a clock generator, two - registers, rewriter shaper, counter, NAND element, the group of information inputs of the timer is connected with the group of information inputs of the first register and the group of information inputs of the second register control input of the first register connected to the first the input of the rewrite signal generator and is the input for recording the timer data; the group of outputs of the first register is connected to the group of information inputs of the counter j whose input is connected With the output of the rewrite signal generator, the second input of which is connected to the counter overflow output, the output of the NAND element is the output of the timer response signal, the control input of the second register is the input of the recording resolution of the timer commands, characterized in that by ensuring the reliability of the information reading during the counting, the multiplexer, the counting pulse generator and the NOT element are entered into the timer, and the group of outputs of the counter is an information group timer outputs, the counter overflow output is the timer interrupt output, the clock generator output is connected to the first information input of the multiplexer, the second information input of which is the timer external clock signal input, the second register output group is the multiplexer control input group, the output which is connected to the first input of the counting pulse generator, the second input of which is connected to the input of the element NOT and is the input of the readout resolution of the timer, The unit is NOT connected to the first input of the NAND element, the second input of which is connected to the output x of the counting pulse generator and to the counting input of the counter. 2. The timer according to claim 1, characterized by the fact that the counting pulse shaper contains three AND-NOT elements and a one-shot, the first input of the counting pulse shaper is connected to the first input of the first IS-NOT element, the second input of which is connected to the first input The second element is NAND and is the second input of the counting pulse generator, the second input of the second element NAND is connected to the output of the third element NAND, the output of the second element NAND is connected to

Description

The third input of the IS-NE and with the input of the one-shot, the output of which is the output of the counting pulse former, the code of the first AND-NO is connected to the second input of the third AND-NOT.

The invention relates to computing and can be used in control number systems for real-time operation.

A timer containing an interrupt register, a microprocessor, a programmable counter, a counter is known, the output of the first counter is connected to the input of a programmable counter, the synchronous input of which is connected to the synchronous input of the timer, the information inputs of the programmable counter are the information inputs of the programmable counter, the output of the programmable counter transition is connected to the control the microprocessor interrupt register input, the information inputs of the counter, and the interrupt register are information inputs of the timer (jj.

A disadvantage of the known device is the possibility of forming only one time sequence diagram.

The most technical to the proposed is a timer containing a generator; two registers, a counter, AND-NOT elements, a rewriter shaper, and the information inputs of the first and second registers are respectively the information inputs of the timer, the outputs of the first register are connected respectively to the first inputs of the W-NOT elements, the second inputs of which are connected to the counter overflow code The outputs of the NAND elements are respectively the timer outputs, the first input of the overwrite signal generator is connected to the timer record input, the second input of the rewriter signal generator is connected to stroke overflow counter and the input of the generator shutdown output signal shaper is connected s.vhodom overwrite recording counter, recording the second input register, input trigger and the output of the generator pj timer interrupt.

A disadvantage of this device is the inability to read information from the counter during counting.

The purpose of the invention is to enhance the functionality by ensuring the reliability of reading information during the counting.

The goal is achieved

the fact that the timer containing the clock generator, two registers, the overwriting signal generator, the counter, the element AND-NOT, and the group

timer information inputs connected to the first register information inputs group and the second register information inputs group that controls the first register input

connected to the first input of the rewrite signal generator and is the enable input of the timer data recording, the group of outputs of the first register is connected to the group of information inputs of the counter, which controls

the input of which is connected to the output of the rewriting signal generator, the second input of which is connected to the overflow output of the counter, the output of the NAND element is the output of the timer response signal, the control input of the second register is the input of the recording resolution of the timer commands, the multiplexer is inserted, the driver

counting pulse and a NOT element, the counter output group is a timer information output group, the counter overflow output is a timer interrupt output, the clock output is connected to the first multiplexer information input, the second information input of the timer timer group the outputs of the second register is a group of control inputs of the multiplexer, the output of which is connected to the first input of the counting pulse generator, the second input of which of the connections to the input of NOT circuit and is input resolution chte audio timer, an output of NOT soediven the first input of AND-NO element whose second input is connected to the output of the pulse output from the meat and counting input of the counter. The counting pulse generator contains three AND-NOT elements and a one-shot, the first input of the counting pulse generator is connected to the first input of the first IS-NOT element, the second input of which is connected to the first input of the second IS-NE element and is the second input of the counting pulse former, the second input The second element AND-NOT is connected to the output of the third element AND-NOT, the output of the second element AND-NOT is connected to the first input of the third element AND-NOT and to the input of the one-shot, the output of which is the output of the counting pulse generator , An output of first AND-NO element is connected to the second input of the third AND-NO. Figure 1 shows the functionality of the timer circuit; figure 2 - functional diagram of the generator counting pulse. The timer contains a register 1, a counter 2, a register 3, a group of 4 information inputs of the timer, a group of 5 information outputs of the timer, an input L of data resolution,: an input 7 of command recording permission, an input 8 of reading resolution, a clock generator 9, a multiplexer 10, form. world clock 11 counting pulse, element I-12, NAND, output 13 of the timer response signal, shaper 14 of the overwrite signal, input 15 of the external clock signal of the timer, output 16. interrupt timer, item 17 is NOT. Shaper counting pulse contains the elements 18, 19 AND-NOT, the one-shot 20, the element 21 AND-NOT. The timer works as follows. The digital value of the specified time interval is recorded from a group of 4 information inputs by pulse at input 6 into register 1 and counter 2. Counter 2 operates in the subtraction mode. The pulses from the clock generator 9 or from the input 15 of the external clock signal through the multiplexer 10 enter the shaper 11 of the counting pulse. On the trailing edge of each pulse, a counting pulse for counter 2 is formed. After counting a predetermined time interval, a pulse appears at the overflow output of counter 2, which reaches the output 16 of the timer interruption and, through the driver, rewrites the digital value of the time interval in counter 2, stored in the register 1. If there is a pulse at the input 8 of the read resolution, it is necessary to prohibit a change in the state of the counter 2. For this, the driver 11 is counting im-. pulse when there is a signal at the input 8 of the resolution and a pulse received through the multiplexer 10, waits for the pulse at the input 8, and then generates a counting pulse that changes the state of the counter 2. When the signal at the input 8 reads during the pulse at the output of the driver 11 counting pulse element AND NOT 12 blocks the signal at the output 13 of the response signal until the end of the counting pulse. The signal at output 13 indicates the presence of reliable information at the output of the counter. Thus, synchronization of the read resolution input 8 and the pulse from the output of multiplexer 10 of the counting pulse generator 11 and blocking the signal at the output 13 of the response signal until the end of the counting pulse by the element 17 is NOT AND NOT of the response signal and reads reliable information from counter 2. The technical advantages of the device are to ensure that reliable information is read out at the time of counting. This makes it possible to simplify the program of work with the timer, which saves the memory of the computer.

1

FIG. 2

Claims (2)

1. A TIMER containing a clock, two registers, rewriter, counter, AND-NOT element, and the group of timer information inputs connected to the group of information inputs of the first register and to the group of information inputs of the second register, control input of the first register connected to the first input of the overwrite signal generator and is an input for recording timer data, the group of outputs of the first register is connected to the group of information inputs of the counter, the control input of which is connected to the output the rewrite signal generator house, the second input of which is connected to the counter overflow output, the output of the NAND element is the output of the timer response signal, the control input of the second register is the enable input for recording timer commands, characterized in that, in order to expand its functionality due to to ensure the reliability of reading information during the counting, a multiplexer, a shaper of the counting pulse and the element are NOT entered in the timer, and the group of outputs of the counter is a group of information outputs timer ode, the counter overflow output is a timer interrupt output, the clock output is connected to the first information input of the multiplexer, the second information input of which is the input of an external timer clock signal, the group of outputs of the second register is a group of control inputs of the multiplexer, the output of which is connected to the first input of the counting shaper pulse, the second input of which is connected to the input of the element NOT and is the input of the permission to read the timer, the output of the element is NOT connected to the first the input of the AND-NOT element, the second input of which is connected to the output of the counting pulse generator and to the counting input of the counter. 2. The timer according to claim 1, characterized in that the counting pulse shaper contains three AND-NOT elements and a single vibrator, the first input of the counting pulse shaper connected to the first input of the first AND-NOT element, the second input of which is connected with the first input of the second AND-NOT element and is the second input of the counting pulse generator, the second input of the second AND-NOT element is connected to the output of the third AND-NOT element, the output of the second AND-NOT element is connected to the first input of the third AND element NOT also with the input of a one-shot, whose output I It wishes to set up the output of the counting pulse, an output of first AND-NO element is connected to the second input of the third AND-NO.