SU1550525A1 - Device for interfacing comimunication channel and computer - Google Patents

Abstract

The invention relates to computing and can be used in telemetry systems for collecting, storing and processing received information. The aim of the invention is to increase speed. The device contains a control unit, two memory blocks, a selector, a synchronization block, an address counter, a register, three switches, three AND elements, an OR element. 1 hp f-ly, 3 ill.

Description

The invention relates to computing and can be used in telemetry systems for collecting, storing and processing received information.

The purpose of the invention is to increase speed.

FIG. 1 shows a diagram of the device; in fig. 2 - block diagram diagram | in fig. 3 is a control block diagram.

The device contains a selector 1, elements AND 2, 3, 4, register 5, address counter 6, switch 7, element OR 8, setup input 9, blocks 10, memory II, synchronization block 12, control block 13, switch 14, switch 15, start input 16 of block 12, second output 17 of block 12, first exit 18 of block 12, input 19 of block 13, input 20 of block 13, input 21 of the initial installation of block 13, first 22 exit

block 13, the third output 23 of the block 13 and the second output 24 of the block 13.

The synchronization unit 12 comprises a generator of 25 pulses, an AND 26 element, a counter 27, a decoder 28.

The control unit 13 contains elements OR 29-31, elements AND 32, 33, triggers 34-36.

The device works in a manner similar to this.

When a signal is applied at input 9 or when the element 8 arrives at the first input, the device is set to the initial state, in which the zero address is set at the output of counter 6, the third 23 and second 24 outputs of the control unit 13 are set to high and low levels . At this time, element 3 permits the passage of a write pulse to memory block 10, switch 14 connects the address input

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the memory block 10 with the output of the address 6 counter, the AND 4 element prohibits the write pulse to the block 11, whose address input is connected to the information receiver's output output using the switch 15, and the switch 7 connects the output of the memory block 11 to the information input of the receiver information.

When a piece of information, which the selector 1 defines as the initial one, appears,

The process is repeated - the data is recorded in the next cell of the memory block 10. When the memory block 10 is full, the output of the overflow of the address counter 6 appears a pulse that enters the control unit 13, where it arrives at the first inputs of the AND elements 32, 33, but the third input of the And element 32 is set to a low level from zero the trigger output 36, so the pulse from the input 19 is fed to the zero input of the trigger 35, while its zero output.

the synchronization signal of the passage of the sync sets a high level to the signal through element 2 I. Moreover, the resolution signal at the output of the selector 1 appears in a certain period of time and gates the synchronization signal. The clock pulse at the output of the element And 2 will fix the data in the register 5 and will start the synchronization block 12. The start of synchronization unit 12 consists in that a pulse with an input goes to the zero input of the trigger 36 and to the first input of the element OR 31, while the trigger 36 changes its state, the third output 23 20 shows a low level, and the second output 24 - a high level, at the output of the element OR 31 a high level appears. After the occurrence of these signals, the element And 3 prohibits the sale of the launch 16 enters the input of the installation of the write pulses to the block 10

counter 27, the output of which appears low level signals, which in turn leads to the appearance of a high level signal at the

the output of the decoder is 28. This signal, Q switch 7 with information input

This allows the passage of signals from the generator 25 pulses through AND 26 to the clock input of the counter 27. As a result, the states at the output of the counter 27 will change, and at the first and second outputs of the decoder 28 sequentially in time appear on the pulse. Moreover, the frequency of following the signals from the pulse generator 25 is chosen such that the time ratios of data establishment at the output of register 5, writing to blocks 10 or 11 of memory, and translation of the address in address counter 6 are observed. The impulse from the first output of the decoder 28 of the synchronization unit 12 through the element 3 is fed to the recording unit memory 10 and records the data set at the output of register 5 at the address set by the address counter 6 and fed through the switch 14 to the address input of the memory unit 10. The pulse from the second output of the decoder 28, the synchronization unit 12 is fed to the counting input of the counter 5 of the address and increases its content by one, which corresponds to the address of the next cell. When the next sync pulse appears, the described pro35

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the information receiver, the AND 4 element permits the passage of write pulses to the memory block 11, the address input of which is connected through the switch 15 to the output of the counter 6 of the address. In addition, at output 22 of block 13, a signal appears indicating that memory block 10 is full. By this signal, the information receiver can proceed to reading the information of the .10 memory block. In this case, the information receiver sets the address of the memory cell from which it is necessary to read information, and reads information from the output of switch 7. After reading the information, the information receiver must give a pulse to input 20 of block 13. This pulse goes to the second inputs of the OR element 29 and 30, from the outputs of these elements, the pulses do not come from single inputs of the flip-flops 34 and 35, while at their single outputs a high level is set, which goes to the inputs of the And 33 and 32 elements, and the zero output of the trigger 35 is set It poured low, which leads to removal of the signal at the output of block 22, 13.

The second goes to the zero input of the trigger 36 and to the first input of the element OR 31, while the trigger 36 changes its state, the third output 23 shows a low level, and the second output 24 - a high level, at the output of the OR 31 element is high. After the occurrence of these signals, element 3 forbids services, the address input of which through the switch 14 is connected to the address output of the information receiver, and the output of memory block 10 is connected via

Q switch 7 with information input

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the information receiver, the AND 4 element permits the passage of write pulses to the memory block 11, the address input of which is connected through the switch 15 to the output of the counter 6 of the address. In addition, at output 22 of block 13, a signal appears indicating that memory block 10 is full. On this signal, the information receiver can proceed to reading the information of the .10 memory block. In this case, the information receiver sets the address of the memory cell from which it is necessary to read information, and reads information from the output of switch 7. After reading the information, the information receiver must give a pulse to input 20 of block 13. This pulse goes to the second inputs of the OR element 29 and 30, from the outputs of these elements, the pulses do not come from single inputs of the flip-flops 34 and 35, while at their single outputs a high level is set, which goes to the inputs of the And 33 and 32 elements, and the zero output of the trigger 35 is set It poured low, which leads to removal of the signal at the output of block 22, 13.

At this very time, from the input of the device, they are recorded into memory block 11 in a manner similar to the process of recording into memory block 10. When counter 6 of the address overflows, an impulse appears at its overflow output, which is fed to control unit 13 and switches trigger 36, if a signal has been given on input 20, which will allow this overflow pulse to pass through AND 32. when input 20 was not sent, trigger 36 will not switch, i.e. subsequent information will be re-recorded in memory block 11. Therefore, to avoid loss of information when outputting from a device, it is necessary that the reading cycle be the king of the information input cycle in the device.

To reset the device to the initial position, it is necessary either to use the setup input 9, or to send a reset pulse from the installation output of the information source.

Claims (2)

1. A device for interfacing a communication channel with a computer, comprising a control unit, a synchronization unit, a register, an address counter, a selector, two memory blocks, a first switch, three AND elements, an OR element, the information input of the register being connected to the information input of the selector and is the input of the device for connecting to the information output of the communication channel, the first inputs of the first AND element and the OR element are the inputs of the device for connecting respectively to the synchronous input and the installation output of the communication channel, the first input is logical The first condition and the first output of the control unit are the input and output of the device for connecting respectively to the interrupt reset output and the interrupt request input of the computer, the information output of the first switch is the output of the device for connecting the information input of the computer, the second input of the OR element is a setup input devices, characterized in that, in order to improve speed, the second and third switches are introduced into it, with the first information input of the second switch connected to 0 five 0 five 0 five 0 five five the first information input of the third switch is the device input for connecting to the address output of the computer; the selector output is connected to the second input of the first element I, the output of which is connected to the register recording input and to the trigger input of the synchronization unit, the counting input of the address counter, the setup input of which is connected to the output of the OR element and the installation input of the control unit, the second input of the logic condition of which is connected to the output of the counter overflow addresses whose output is connected to the second information inputs of the second and third switches, whose information outputs are connected respectively to the address inputs of the first hour of the second memory block, whose information outputs are connected to the first and second information inputs of the first switch, respectively, the control input which is connected to the control input of the third switch, to the second output of the control unit and to the first input of the second element I, the output of which is connected to the recording input of the second block n The information input of which is connected to the information output of the register and to the information input of the first memory block whose recording input is connected to the output of the third element I, the first input of which is connected to the control input of the second switch and the third output of the control unit, the second sync output of the block synchronization is connected to the second inputs of the second u of the third element I. 2. The device according to claim 1, characterized in that the control unit includes three flip-flops, three OR elements, two AND elements, the first input of the first OR element is connected to the first input of the second OR element, to the first single input of the first trigger and is the installation input of the block, the second input of the first OR element is connected to the second input of the second OR element, and is the first input of the logical condition of the block, the first input of the first And element is connected to the first input of the second And element, and is the second input of the logical condition blo a, the output of the third OR element is the first output of the block, the zero output of the first flip-flop is connected to the second input of the first element And is the second output of the block, the single output of the first flip-flop is connected to the second input of the second element And, and is the third output of the block in the control unit, the outputs of the first and second elements OR are connected respectively to the single inputs of the second of the third and third triggers, the zero inputs of which are connected respectively to the outputs of the first and second elements And, the third inputs of which are connected respectively to the single outputs of the third and second triggers, zero outputs of which are connected respectively to the zero and second single inputs of the first trigger, as well as the first and the second inputs of the third element OR " 1 J Fig 2