SU1589288A1 - Device for executing logic operations - Google Patents

Abstract

The invention relates to computing and can be used in specialized systems for the logical processing of information arrays (sets). The purpose of the invention is to expand the functionality by performing intersection, addition, and union of disordered sets. The device contains a decoder 1, a group of elements OR 2, a register 3, a decoder 4, a group of elements OR 5, a register 6, a group of elements AND 7–9, a group of elements NOT 10, a group of elements AND 11, a group of elements OR 12, a group of elements AND 13 , element OR 14, group of elements OR 15, group of elements AND 16, decoder 17, element OR 18, element AND 19, delay element 20, element AND 21, pulse generator 22, resolution addition inputs 23, device intersection 24, counter 25 , memory block 26, element OR 27, initial setup input 28, initial setup installation input 29 operation, write enable input elements of the first 30 and second 31 sets of device input 32 read the result, the first 33 and second 34 data inputs of the device, the result output device 35, output device 36 indicating completion of the operation. The goal is achieved by introducing new elements and connections. 1 il.

Description

The invention relates to computing technology and can be used in specialized systems for the logical processing of information arrays (sets).

The purpose of the invention is to expand the functional capabilities by performing 25 intersection, addition, and combining randomized operations.

sets.

The drawing shows the functional diagram of the device.

The device contains a decoder, a group of elements OR 2, register 3,. decoder 4, group of elements OR 5, register 6, group of elements AND 7–9, group of elements NOT 10, group of elements AND 11, group of elements OR 12, group of elements And 13, element OR 14, group of elements OR 15, group of elements AND 16, decoder 17, element OR 18, element DOS AND 19, delay element 20, element 21, pulse generator 22, resolution addition input 23, device intersection 24, counter 25, memory block 26, element OR 27, input dz 28 initial installation of the device, input 29 of the initial installation of device operation, the inputs of the recording resolution ementov first 30 and second 31 sets of device input 32 result reading apparatus, the first 33 and second 34 data inputs of the device, the result output device 35, output device 36 indicating completion of the operation.

The device works as follows.

In the initial state, the operation of the device for the execution of operations is blocked by signals O at inputs 23 and 24. At inputs 33 and 34, there is no information. Timing signals at inputs 30, 31 are missing. Logic 1 is provided to the device input 28, which provides the initial setting of registers 3 and 6, as well as through the OR element 27 - the initial setting of the address counter of memory block 26 and counter 25, Registers 3 and 6 store O, the memory block 26 stores O all bits and cells, at the input of the element And 21 also O, blocking the operation of the counter 25 and the recording of information in the memory block 26.

The initial information about the composition of the set operands A and B in the form of the codes of their elements, A. and b; b comes to the inputs .33 and 34 of the device, respectively, after removing the initial setup signal from the input 28. At the same time, each code set corresponds to the element of the set A, is synchronized by 1 at input 30, corresponding to the element of set B - at input 31, which ensures the fixation of the result of combining the previous code with the current one in registers 3 and 6, respectively. The code fixed in each of the registers has the form Og d,.,. d, where 1 is the number of the input clock matsii; dj is 1 if the element encoded by i belongs to the set and dJ O otherwise. The formation of D g is carried out by a group of elements OR 2 for the set A and a group of elements OR 5 for the set B by the formula Dg D. UD, where D-g is the current code from the outputs of the decoder 1 for the set Lis of the outputs of the decoder 4 for the set B to

1st tact fixation. This code is of the form D 0,0 ... 1.0;, .. 0, where i is the code value of the element at the input of the decoder 1 for the floor of the Ai decoder 4 for the set B, Thus, in registers 3 and 6 position codes are fixed Vd and Dg, containing 1 in bits with numbers equal to the value codes of the elements

of sets A and B.

After the transmission of the codes of the elements of the first set A and the second set B is completed, signals O are set on the inputs 30 and 31 of the device, blocking the change in the contents of registers 3 and 6; From the information outputs of registers 3 and 6, the codes AT and D g arrive at the inputs of the group of elements AND 7 where the VdPVz operation is performed. The result is fed to the inputs of the group of elements NOT 10, where the operation D is performed, the Code D e goes to the first inputs of the group of elements AND 8 and to the first inputs of the group of elements AND 9. The second inputs of the group of elements And 8 receive the code Here, here The A / B operation is performed and the second inputs of the And 9 group of elements receive the Dg code, the DP5 operation is performed here, and both of these results go to the inputs of the And 12 group of elements, where the A + B operation is performed. Thus, at the outputs of the OR 12 element group. there is a code, the result of adding the sets A and B, and at the outputs of the group of elements And 7 there is a code D d, c of the result of intersection of the sets A and B, for decoding and storing information in the memory block 26 at the inputs

23 and 24, the following operation codes are set: input 23 - 1, input

24-o for addition operation;

input 23 - O, input 24 - for an intersection operation; input 23-1, input 24-1 for the merge operation. When signal O at input 24, signal 1 at input 23 opens a group of elements AND 13, whose inputs receive a code and through the group, elements OR 15 are fed to the second inputs a group of elements AND 16, 1 at input 23 through the element OR 14 open also passes the signal from the generator 22, through the element 21 of the synchronizing operation of the counter

25i through the delay element 20 post1 892

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element 19, which is fed to the second input, decoding and writing to the memory block 26 the result of the addition operation is carried out in the following manner. Upon receipt of the clock signal from the generator 22, the counter 25 starts counting. The contents of the counter are converted in the decoder k 1 to the position code and fed to the first inputs of the group of elements 16, which is compared with the code Od. The result is given to the inputs of the elements of IL 18. The presence of 1 at least on one of the inputs of the element 15 or 18 means the presence of the current code from the decoder 17 in the result code 25

Tata operation Add Od. and generates a signal of logical 1 at the first input of the element And 19, opening it for

20 clock pulse delayed by element 20 from generator 22. The delay time on element 20. is selected taking into account the response time of counter 25, decoder 17, AND 16 group of elements and OR 18 element. 26 memory, the signal from generator 22 provides recording of the current element from the outputs

30 counter 25 in memory block 26. In each subsequent cycle from the counter 25, the decoder 17 receives the value of the next element, which causes its code to match at least one

35 by position1.1 of the result code, recorded in memory block 26. If there is no match, then the current element is not written to memory block 26, since AND 19 is closed by a logical O c

0 of the output of the element OR 18 and the memory unit 26 is not supplied with a write-back signal. At the time of the counter overflow

25 a signal is output to output 36, after an O signal is received from input 32 it can

5 reading from the output of 35 elements of the set C, resulting from the addition of sets A and B. To perform another type of operation without changing the initial information, it is enough to send a signal 1 to the input 29, which will provide the initial setting of the block address.

26, and a counter 25. Then, for example, an operation intersects the NIN sets A. and B. At the inputs 23 and 24 of the device, the combination O, 1 is applied, which opens the group of elements AND I1 to pass through the group of elements OR 15

The result code of the intersection operation Aiff D, similarly to the above, decrypts and writes into memory 26 the elements of the set C, which is the result of intersection of the sets A and B. When choosing the combination of the combination and the inputs .23 and 24 of the device, combination 1, 1 is fed, which ensures entry to the first entrances

the groups of elements OR 15 of the code Od, i and on the second inputs - the code Vd, and: the operation Рдцв is performed here

ten

A-tB VB is then similarly carried out by depgafraction and recording by BI of block 26 of the memory of the elements of set C, resulting from the union of sets A and B. Before updating the initial information about the sets of operands, the device is blocked by the signal O at inputs 23, 24 and a signal 1 is applied to the input 28 of the device. Signals at inputs 30.31 are missing. The device is ready to receive new information ,,

Claims (1)

Invention Formula 15 20 25 35 40 A device for performing logic operations / containing a counter, a decoder, an optical unit, a pulse generator, two OR elements, two AND elements, two registers, characterized in that, in order to enhance the functionality by performing intersection, addition and combining disordered sets, two decoders are introduced into it, four groups of OR elements, six groups of AND elements, a group of NOT elements, a delay element and an OR element, with input 1.1 of the first and second decoders connected to the primary Mu and the second information inputs of the device, the outputs from the first to the M-th first decoder are connected respectively to the first inputs of the elements of the first group from the first to the M-th, outputs from the first to the M-th second rator are connected respectively to the first inputs of the OR elements of the second group with the first by outputs of the OR elements of the first and second groups are connected to the information inputs of the first and second registers, respectively; the outputs from the first to the M-th first register are connected to the corresponding 1589288. but to the second inputs of the elements OR of the first group from the first to the M-th, to the first inputs of the elements AND of the first group from the first to the M-th and to the first inputs of the elements AND of the second group from the first to the M-th, outputs from the first to the M-th The second register is connected respectively to the BTOpL-M inputs. the elements OR of the second group from the first to the M-th, to the second inputs of the elements AND of the first group from the first to the M-th and to the first inputs of the elements AND of the third group from the first to the M-th, the outputs of the elements AND of the first group from the first to M- th are connected to the inputs of elements NOT groups from the first to the M-th, to the first inputs of the elements AND the fourth group from the first to the M-th, the outputs of the elements NOT from the first to the M-th are connected respectively to the second inputs of the elements AND the second group from the first to M and to the second inputs of the elements of the third group, from the first to the M-th, the outputs of the elements of the second and A network of groups is connected respectively to the first and second inputs of the K-th element OR of the third group (K 1, M), the output of which is connected to the second input of the K-th element AND the fifth group, the first input of which is connected to the first input of the first element OR , the second input of the first element OR is connected to the second inputs of the element AND of the fourth group, the outputs of the Kx elements AND of the fourth and fifth groups are connected respectively to the first and second inputs of the K-th element OR of the fourth group, the output of which is connected to the first input of the K-th element And the sixth group, in the second input of which is connected to the K-th output of the third deshIl-rator, the output of the K-th element of the sixth group is connected to the K-th input of the second OR element, the output of which is connected to the first input of the first element And, the output of the second element And through the delay element connected to the second input of the first element AND, the first and second inputs of which are connected respectively to the output of the pulse generator and to the output of the first element OR, the first and second inputs of which are connected respectively to the enable inputs of the operation of addition and resolution of operation the intersection of the device, the output of the second element And is connected to the synchronous input of the counter, the output of which is connected to the input of the third 45 50 55 the decoder and the information input of the memory block, the output of the first element I is connected to the sync input of the memory block, the input of the initial setting of the address of the memory block and the input of the initial installation of the counter are connected to the output of the third element OR, the first input of which is connected to the inputs of the initial installation of the first and the second register and to the input of the initial installation of the device, the second input of the third element OR is connected to the input of the initial set device resolution inputs of the first and second registers are connected respectively to the write enable inputs of the first and second device sets, the read synchronization input of the memory block is connected to the read input of the device, the output of the memory block is connected to the output of the device, the overflow output the counter is connected to the output indication of the end of the operation of the device.