SU1656514A2 - Timer - Google Patents

Abstract

The invention relates to computing and can be used in control computing systems for real-time operation. A distinctive feature of the timer is that it provides the reading of reliable information from the counter during counting, without requiring selection by the duration of the data readiness signal at the computer input. The aim of the invention is to increase reliability by ensuring reliable formation of a timer readiness sign. This is achieved by the introduction of delaying and prohibiting elements 18 and 19. 2 Il.

Description

The invention relates to computing and can be used in control computing systems for real-time operation.

The purpose of the invention is to increase reliability by ensuring the reliable formation of a sign of readiness of the timer.

Figure 1 shows the timer circuit; figure 2 - the timing diagram of his work.

The timer contains a data register 1, a time interval counter 2, a command register 3, a group of 4 information inputs for a time interval, a group of 5 information outputs, a data recording permission input 6, a command recording permission input 7, a read permission input 8, a clock generator 9, a multiplexer 10, counting pulse generator 11, NAND element 12 with output 13, overwriting signal generator 14, external timer clock input 15, timer interrupt output 16, HE element 17, element 18

delay, the element 19 of the ban, the output 20 readiness timer.

As a shaper 14 of the rewriting signal, you can use a single-vibrator, for example, based on 533 AGZ with a logical element OR at the input.

The timer works as follows.

A code of a specified time interval from a group of 4 information inputs on a signal from input 6 of recording resolution is recorded in data register 1 and a counter 2. In register 3 commands on a signal from input 7 of recording resolution, a command code that controls multiplexer 10 is recorded. Pulses of a clock generator 9 or the pulses from the input 15 of the external clock signal through the multiplexer 10 enter the shaper 11 of the counting pulse. On the leading edge of each pulse at the output of the multiplexer 10 in the generator 11 of the counting pulse a negative pulse is generated for counter 2. Counter 2 operates by changing the signal at the counting input from one

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state to zero. After counting a predetermined time interval, a pulse appears at the overflow output of counter 2, which arrives at the output of timer interrupt 16 and restores the digital value of the time interval in counter 2 stored in data register 1 via the overwrite signal generator 14. When a read permission signal (low level) appears at input 8 and a counting pulse is not present at the output of generator 11, the prohibition elements 12 AND-NOT and 19 are opened and a signal (low level) is generated at the timer output 20, which is a sign of timer readiness.

In order to ensure reliable reading of timer information during counting, the sign of timer readiness must be generated at times when counter 2 is not transient due to transfer spread after a counting pulse arrives at its input.

This requirement in the timer circuit is provided as follows.

In the absence of a read resolution signal (high level) at input 8, each time the level changes from low to high at the output of multiplexer 10 (frequency F), the shaper 11 of the counting pulse with some delay g produces a zero polarity pulse arriving at the input of the counter 2 and the second input element AND NOT 12.

If the read enable signal appears at the input of the NAND 12 element outside the interval r, counted from the leading edge of the frequency F pulse, then the low level signal at the output 20 indicates the presence of reliable information at the output of the counter 2. Thus, when the counting pulse of the read resolution signal (low level) appears at the inputs of the generator 11 before the leading edge of frequency F at the output of the multiplexer 10, the counting pulse generator 11 waits for the end of the read permission signal, and then generates a counting pulse changing

the state of the counter 2. If the read resolution signals and the counting pulse at the output of the imaging device 11 coincide, the NAND element (see Fig. 2) will be closed

low level from the output of the former 11. At the completion of the counting pulse, the element AND-NO 12 opens, a low level at the output of the IS-NOT 12 opens the prohibition element 19 and at its output a signal appears

low level, which is a sign of timer readiness.

Another case is possible when the read input signal arrives at the first input of the NAND 12 element at the interval g

relative to the leading edge of the pulse frequency F (see Fig.2). In this case, since the low level of the second input of the NAND 12 element is not yet formed (from the output of the imaging unit 11 of the counting pulse),

Claims (1)

At the output 13 of the element IS-NOT 12, a low level interference signal appears. The duration of the interference will not exceed t. However, the prohibition element 19 will be closed by a low signal from the output of the delay element 18. If the delay value of the element 18 is chosen not less than t, then the opening of the prohibition element 19 (i.e. the appearance of the timer readiness sign) will occur after the termination of the interference signal at the output 13 of the AND-NO element 12, i.e. The readiness indicator of the timer will be generated after the guaranteed completion of the transient processes in counter 2 (see figure 2). Invention Formula Timer auth. N; 1142822, characterized in that, in order to increase the reliability of the timer by ensuring reliable formation of the readiness attribute, a delay element is introduced into it and a prohibition element, the input of the delay element is connected to the output of the NOT element, the output of the delay element is connected to the information input of the prohibition element whose control input is connected to the output of the NAND element, the inverse output of the prohibition element is the output of the timer data readiness. Out.20