SU1605244A1 - Data source to receiver interface - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated control devices as a memory buffer device. The aim of the invention is to increase the speed of information exchange between the source and receiver of information. The device contains an input register, a switch, six delay elements, seven AND elements, two OR elements, an OR-NOT element, two triggers, two decoders, two reversible counters, a comparison circuit, a two-bit counter, and a memory block. 1 il.

Description

The invention relates to automation and computing and can be used in automated control devices as a buffer memory device.

The purpose of the invention is to increase the speed of information exchange between the source and receiver of information.

The drawing shows a block diagram of the device.

The device contains an input register 1, switch 2, the first delay element 3, the third delay element 4, the second element 5 in-. supports, second 6 and first 7 elements OR, comparison circuit 8, first 9 and second 10 reversible address counters, first trigger 11, first 12 and second 13 elements AND, memory block 14 containing the second decoder 15, first decoder 16, block 17 elements OR, N information registers 18 of the first group, N blocks 19

elements And the first group, N blocks 20 elements And the second group. The device also comprises a third element AND 21, a fourth element And 22, a fifth element And 23, a sixth element And 24, a seventh element And 25, an OR-FIE 26 element, a fourth delay element 27, a fifth delay element 28, a sixth delay element 29 , second trigger 30. two-digit counter 31 ,. In memory block 14, information shift is performed using (N-1) information registers 32 of the second group, (N-I) blocks 33 elements AND of the fourth group, (N-1) blocks 34 elements AND of the third group.

In addition, the diagram shows: device information input 35, device recording gating input 36, device reading gating input 37, device installation setting 38, device information output 39, output 40 ready (L

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write, read-ready device output 41, Device Sync A2 input.

The device works as follows.

The code set on the counter 10 determines the address of the register 18 of the block 14, to which information is recorded upon next access to the device in the recording mode. The selection of the i-ro register 18 of block 14 in this mode is made by the resolving potential at the i-M output of the decoder 15.

The code set on the counter 9 determines the address of the register 18 of the block 14, from which information is read in the next access to the device in the read mode. The i-ro selection of register 18 of block 14 in this mode is made by the resolving potential at the i-M output of the decoder 16.

Writing (reading) information into the i-th register 18 of block 14 is performed sequentially, in order of increasing addresses of registers 18 of block 14. After writing (reading) to the i-th register 18 of block 14, the contents of the counter 10 (9) are added to unit and, thus, sets the code corresponding to the address (i + 1) -ro of the register 18 of block 14,

Requests for writing and reading information are received into the device asynchronously, therefore, during operation of the device, information is provided only from those registers 18 of block 14 to which recording was made. This is achieved by fulfilling the condition of the contents of the counter 9 of the contents of the counter 10. If the contents of the counter 9 become equal to the contents of the counter 10, then at the output of the comparison of the comparison circuit 8 the zero level is set, which through the OR element 6 enters the AND 13 element and through the AND 24 element output 41 of the device and prohibits reading the information. Reading the information becomes possible after increasing the contents of the counter 10, i.e. after the next write to the device.

When writing information to all N registers 18 of block 14 and the absence of reading signals, counter 10 becomes zero when overflow occurs after writing information to the Nth register 18 of block 14, In this case, the signal.

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allowing the reading of information from the device is generated when the overflow signal of counter 10 appears, which triggers trigger 11. The unit potential at the forward trigger output enters through the OR element 6 and the AND 24 element at the output 41 of the device and allows the control signal to pass reading.

The trigger 11 is reset to the initial state after reading the information from the last register 18 of the block 14. At the same time, the overflow signal of the counter 9 is generated, which, arriving at the OR element 7, performs actions similar to the initial setting signal.

Writing to the device is blocked from the moment the counter 10 overflows until the counter 9 overflows (i.e., between writing to the last Nth register 18 and reading information from it). To reduce the time lost associated with this blocking, the device shifts the information contained in the N registers 18 of block 14 in the direction of the registers 18 of block 14 with lower addresses after reading the information from the latter. The information is shifted using the registers 32 of the block 14 in the absence of read and write requests to the device. In the shift mode, the trigger 30 is set to one, which results in a ban. read and write to the device at the time of the shift and to start the counter 31, which controls the shift process.

At the completion of two clock cycles (clock — recording information from i-ro register 18 of block 14 into (i-1) -th register 32 of block 14 (i 1, N), 2nd cycle — recording information from j-th register 32 block 14 into the j register 18 of block 14, 3 1 N-1) from the contents of counters 9 and 10. one is subtracted and trigger 30 is reset. The shift operation is repeated until a high potential appears at the first output of the decoder 16, which indicates choosing to read the first register 18 of block 14 and, therefore, about the absence of registers 18 of block 14, from which information has already been read.

With frequent follow-up requests for reading and writing infornacin into the device and, therefore,

It is possible that the shift in information is difficult to overflow with a striker 10. In this case, carrying out shifts is blocked until the trigger is reset. 11.

Before starting operation, a two-bit counter, counters 9 and 10, registers 18 or 32 of block 14 are reset by the pulse signal at the input 38 of the initial installation of the device and the trigger 11 is reset to the initial state, which forms the readiness of the device at output 40. When reset, zero codes are entered into counters 9 and 10 and, due to the equality of the contents of these counters, a zero level is set at the output of the comparison of the comparison circuit 8, which prohibits the reading of information from the device.

When entering information, the write control signal is fed to the device input 36 and allows the information from the device input 35 to pass through the switch 2 to the data register 1, register 1 receives the information signal to the input of the blocks of the 19 elements, and the recording signal after the delay on the element 3 delays at the input of the element And 12 comes from the output of this element to the input of the blocks of the 19 elements I. The information is written into the corresponding register 18 of the block 14 when the enabling signal is present at the corresponding output of the decoder 15, After delay element 5 of delay time of recording information in the register 18, a write signal, the counter 10 increases by one, whereby via the decoder 15 may be selected the next block register 18, 14,

Increasing the content of the counter 10. in the process of recording information leads to the appearance of a single level at the output of the comparison of the comparison circuit 8, which through the OR element enters the AND 13 elements and allows the read control signal to pass to the inputs of the AND elements of the blocks 20,

The information is read when the read control signal arrives at the input 37. In this case, the reading is carried out sequentially from the registers 18 of the block 14. The information signal from the register 18 through the block 17 of the elements OR is fed to info 6052446

formational output 39 devices. In addition, the read control signal after a delay on the delay element 4 by the read time from the register 18 increases the contents of the counter 9 by one, as a result of which the next register 18 is selected for reading using the decoder 16,

Q Information shift is performed as follows. In the absence of control signals for writing and reading, high potentials at the direct output of the trigger 11 and the first output of the decoder 16 of the encoder 16, a high potential appears at the output of the OR-HE element 26, which through the AND 24 element designed to eliminate the forbidden combinations at the trigger input 30, post 20 goes to a single trigger input 30. Upon the arrival of the clock pulse, the trigger 30 is transferred to a single state (FIG. 2), which leads to a reset of read and write readiness at device outputs 40 and 41 and to allow the delayedthe transfer time of the trigger 30 sync pulses to the counting input of the counter 31,

30 When the first bit of the first counter of the counter 31 is set, information from the i-ro register 18 is recorded into (1-1) -th register 32 (i 1, N), and when the second bit is set to the single bit of the second bit 31 - entry from j-ro register 32 to j register 18 (j 1, (N-1)), Last Nth register 18

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in doing so, it is zeroed.

The delay elements 27 and 29, which delay the signals for the same time, are designed to ensure the reset of the counter 31 and the trigger 30 by the following sync pulse after the sync pulse for which the second bit of the counter 31 is set to one, the reset of the trigger 30 leads to the restoration of read and write readiness at outputs 40 and 41 devices.

If the information is written to the last Nth register 18, this leads to overflow of counter 10, the overflow signal of this counter sets the trigger 11 to one state, which leads to a reset of readiness to write at the output 40 of the device and to the prohibition of conducting shifts.

After reading information from the last N-ro register 18 of block 14, an increase in the content of counter 9 by one results in the appearance of a signal of its overflow, which, entering the input of the element OR 7, brings the device to the initial state.

Claims (1)

Invention Formula A device for interfacing the source and receiver of information containing the input register, switch, first, second and third delay elements, first and second elements ILI comparison circuit, first trigger, first and second elements AND, first and second decoders, block OR elements, N information registers of the first group, N blocks of AND elements of the first group, N blocks of AND elements of the second group, the first input of the first OR element is the input of the device initial setup, the output of the first OR element is connected to the input of the ne installation The first trigger, with the setup inputs (N-1) of the information registers of the first group and the first setup input of the Nth information register of the first group, the switch's information input group is a group of device inputs for connecting to the information source information buses, allowing the switch input combined with the input of the first delay element and is the input of the device for connecting the output of the information source record to the output; the output of the switch is connected to the information input of the the register, the outputs of which are connected to the first inputs of N blocks of elements of the I group, the outputs of which are connected to the first groups of data inputs of N information registers of the first group, the outputs of which are connected to the first inputs of N blocks of elements of the second group, the outputs of which are connected to the corresponding inputs of an OR block whose output is the output of a device for connecting one to the information input of the first information receiver, the outputs of the first decoder are connected to the second inputs of the N blocks of elements AND the second groups, the output of the first delay element is connected to the first input of the first element AND, the output of which is connected to the second inputs of N blocks of elements AND of the first group and to the input of the second delay element, the direct and inverse outputs of the first trigger are connected respectively to the first input of the second OR element and the second input of the first element is AND, the output of the second element OR is connected to the first input of the second element AND, the second input of which is the input gate of the device reading, the output of the second element AND is connected to the third inputs of N blocks e In the second group and with the input of the third delay element, the output of the comparison circuit is connected to the second input of the second OR element, the outputs of the second decoder are connected to the third inputs of the N blocks of the AND elements of the first group, that, in order to increase speed, two reverse address counters are inserted in the device, the third, fourth, fifth, sixth and seventh AND elements, the OR-NOT element of the fourth, fifth and sixth delay elements, the second trigger, two-digit counter, N- 1 information registers of the second group, N-1 b the shackles of the elements of the third group and N-1 blocks of elements of the fourth group, the output of the first element OR is connected to the first input of the two-bit counter installation, to the installation inputs of the first and second address counters and to the inputs of the N-1 installation of information registers of the second group to the fourth The delay element is connected to the installation input of the second trigger, with the first input of the third element I, with the first inputs N-1 of the blocks of elements AND of the third group, with the second installation input N-ro of the information register of the first group and with the input The subtraction of the first and second address counters, the outputs of the second and third delay elements are connected to the counting addition inputs of the second and first address counters, respectively, the information inputs of the second address counter are connected to the inputs of the second decoder and the first group of comparison circuit inputs, the information outputs of the first address counter are connected with the inputs of the first decoder and with the second group of inputs of the comparison circuit, the overflow outputs of the first and second counters the addresses are connected respectively to the second input of the first OR element and to the reset input of the first trigger; the inverse output of the first trigger is connected to the first input of the fourth AND element integrated with the second input of the first element AND, the output of the fourth element AND is the read write output of the device, the input of the first element the delay is combined with the first input of the element OR NOT, the output of which is connected to the first input of the fifth element AND, the output of which is connected to the reset input of the second trigger, the inverse output of which is connected to the fourth input of the fourth element AND, the first input of the sixth element AND, the output of which is the readiness output of the device, the output of the second element OR is connected to the second input of the sixth element AND, the second input of the second element AND is connected to the second input of the element OR NOT, direct the output of the first trigger is connected to the third input of the element OR NOT; the first output of the first decoder is connected to the fourth input of the element SH-NOT; the sync bypass of the second trigger is the synchronization of the device and is connected to the input of the fifth delay element the second input of the third element I, the output of which is connected to the second input of the installation of a two-bit counter, the direct output of the second flip-flop is connected to the first input of the seventh element I, the output of which is connected to the counting input of the two-bit counter, the direct output of the first digit of which is connected with the first input of N-1 blocks of elements And the fourth group, 0 direct and inverse outputs of the second bit of a two-bit counter are connected respectively to the input of the fourth delay element and to the input of the sixth delay element, the output of which is connected to the second input of the fifth And element, the output of the fifth Delay element is connected to the second input of the seventh And element , outputs of N-1 blocks of elements And the fourth group 0 connected to the data inputs N-1 information registers of the second group, the outputs of which are connected to the second inputs of the N-1 blocks of elements And the third group, the second group of inputs 5 data of the i-ro information register of the first group, where i 1 ... (N-1) is connected to the information outputs of the i-ro block of elements of the third group, where i 1 ... N-1, the second inputs 0 of the block of elements AND of the fourth group, where j 1., .N-1, are connected to the second group of data outputs (j + 1) -ro of the information register of the first group. 0 -O JO o 35 oJ8 33