NL1037063C2

NL1037063C2 - SEMICONDUCTOR CHIP, WHICH IS MANUFACTURED IN A SEMICONDUCTOR SUBSTRATE TRANDFER / TUNING TUNNEL INSTALLATION FOR THE PURPOSE OF OPERATING THERE FOR THE UNINTERRUPTED PLACE OF A TOTAL SEMICONDUCTOR DEPARTMENTAL DISPRODUCTIONAL DEPROCESSIONAL DISPRODUCTIONAL DEPROCESSIONAL DEPROCESSIONAL DISPRODUCTIONAL DEPROCESSIONAL DISPRODUCTION DEPROCESSED SEPARATION DEPROCESSING SEPARATE DEPROCESSING SEPARATE SEPARATE DISPRODUCTION DEPROCESSIONAL SEPARATE SEPARATE SEPARATE DISPRODUCTION DEPROCESSED SEPARATE SEMICONDUCTOR CHIP.

Info

Publication number: NL1037063C2
Application number: NL1037063A
Authority: NL
Inventors: Edward Bok
Original assignee: Edward Bok
Priority date: 2009-06-23
Filing date: 2009-06-23
Publication date: 2010-12-27

Description

Semiconductor chip, welke is vervaardigd in een semiconductor substraat trandfer/behandelingstunnel-opstelling ten behoeve daartoe tijdens de werking ervan het ononderbroken plaatsvinden van een totaal semiconductor behandelingsproces van de daarin 5 ononderbroken verplaatsende semiconductor substraat.Semiconductor chip, which is manufactured in a semiconductor substrate trandfer / treatment tunnel arrangement for this purpose during the operation thereof of the continuous occurrence of a total semiconductor treatment process of the semiconductor substrate continuously moving therein.

In zulk een semiconductor installatie vindt typisch de enorme jaarproductie van circa 0.4 miljard semiconductor chips plaats.In such a semiconductor installation, the enormous annual production of approximately 0.4 billion semiconductor chips typically takes place.

Zulk een semiconductor installatie is tot op heden nog niet bekend.Such a semiconductor installation is as yet unknown.

10 Daarbij verder de reeds in de bijgaande Nederlande Octrooi-aanvragen van de aanvrager ontschreven hoofdvoordelen van zulk een nieuwe semiconductor installatie ten opzichte van de bestaande semiconductor installaties onder toepassing van tenminste mede individuele semiconductor modules en - wafers.10 In addition, the main advantages of such a new semiconductor installation as described in the attached Netherlands Patent Applications of the applicant compared to the existing semiconductor installations using at least co-individual semiconductor modules and wafers.

15 De typisch minder dan 15 meter lange semiconductor installatie heeft daarbij slechte een breedte van typisch minder dan 2 meter ten behoeve van daarin tijdens de werking ervan de bewerkstelliging van zulke semiconductor chips uit opvolgende semiconductor substraat-gedeeltes.The semiconductor installation, typically less than 15 meters long, then has a width of typically less than 2 meters for the purpose of bringing about such semiconductor chips from successive semiconductor substrate portions during operation thereof.

Daarbij in zulk een installatie de opname van tenminste mede een 20 semiconductor substraat transfer/behandelingstunnel-opstelling, welke verder in deze aanvrage is omschreven en waarin tijdens de werking ervan in opvolgende semiconductor behandel ingssecties het ononderbroken plaatsvinden van opvolgende semiconductor behandelingen van de opvolgende, zich ononderbroken erdoorheen verplaatsende 2 5 semiconductor substraat-gedeeltes en zulks typisch onder toepassing van een ononderbroken folie als tenminste tijdelijke semiconductor onderlaag ervan.In such an installation the inclusion of at least partly a semiconductor substrate transfer / treatment tunnel arrangement, which is further described in this application, and wherein during its operation in successive semiconductor treatment sections the continuous occurrence of successive semiconductor treatments of the successive uninterrupted moving semiconductor substrate portions therethrough and typically using a continuous film as at least temporary semiconductor substrate.

In een volgende gunstige uitvoering van deze semiconductor installatie daarin de opname van een inrichting ten behoeve van de opslag van een 30 zodanig zeer lange folie, dat gedurende een zeer lange tijd, typisch tenminste circa 0,2 jaar, een tenminste nagenoeg ononderbroken lineaire verplaatsing ervan door zulk een semiconductor tunnel-opstelling geschiedt.In a further favorable embodiment of this semiconductor installation, the incorporation therein of a device for the purpose of storing such a very long film that for a very long time, typically at least approximately 0.2 years, an at least substantially continuous linear displacement thereof by such a semiconductor tunnel arrangement.

Verder bevat zulk een folie evenwijdige opstaande zijwanden en heeft deze een breedte, welke in geringe mate kleiner is dan die van de 35 doorgang van zulk een tunnel-opstelling.Furthermore, such a foil comprises parallel side walls and has a width which is slightly smaller than that of the passage of such a tunnel arrangement.

In een gunstige uitvoering is zulk een tunnel-opstelling ononderbroken en strekt zich uitsluitend in lineaire richting uit.In a favorable embodiment, such a tunnel arrangement is continuous and extends exclusively in a linear direction.

Daarbij ie de doorgang ervan te» behoeve van tenminste de verplaatsing erdoorheen van de opvolgende semiconductor substraat-gedeeltes tijdens de 1037063 2 werking alleen ter plaatse van de in- en uitgangszijde ervan in open verbinding met de atmospherische buitenlucht onder toepassing van een gasvormig mediumslot aan tenminste de ingangszijde ervan.Thereby the passage thereof for at least the displacement therethrough of the successive semiconductor substrate portions during the 1037063 2 operation only at the location of the input and output side thereof in open communication with the atmospheric outside air using a gaseous medium slot on at least its entrance side.

Verder in een gunstige uitvoering van deze installatie achter zulk een 5 tunnel-opstelling de opname van een inrichting ten behoeve van daarin tenminste mede door deling van de opvolgende, daarin ononderbroken semiconductor behandelde semiconductor substraat-gedeeltes, de bewerkstelliging van zulke semiconductor chips.Furthermore, in a favorable embodiment of this installation behind such a tunnel arrangement, the incorporation of a device for at least partly by dividing the subsequent semiconductor substrate parts treated therein, the realization of such semiconductor chips.

Verder bevat deze installatie middelen ten behoeve van de besturing 10 van tenminste mede de opvolgende semiconductor behandelingen in zulk een tunnel-opstelling en het semiconductor substraat transfersysteem ten behoeve van een tenminste nagenoeg ononderbroken gelijkmatige verplaatsing van de opvolgende semiconductor substraat-gedeeltes erdoorheen.Furthermore, this installation comprises means for the control of at least partly the subsequent semiconductor treatments in such a tunnel arrangement and the semiconductor substrate transfer system for an at least substantially uninterrupted uniform displacement of the subsequent semiconductor substrate sections therethrough.

Voor deze installatie personeel ten behoeve van het plaatsvinden van 15 tenminste mede het navolgende; a) het opstarten van de werking van zulk een semiconductor tunnel-opstelling en beëindiging ervan; en b) controle van de correcte continue werking van deze tunnel-opstelling en het onderhoud ervan.For this installation personnel for the purpose of taking place at least partly the following; (a) the start-up and termination of such a semiconductor tunnel set-up; and b) checking the correct continuous operation of this tunnel setup and its maintenance.

20 Verder bevat deze installatie inrichtingen ten behoeve van het navolgende: a) starten en beëindigen van de toe- en afvoer van de semiconductor behandelingsmediums en de transfermediums; en b) onderhouden van een continue toe- en afvoer van deze mediums.Furthermore, this installation comprises devices for the following: a) starting and ending the supply and discharge of the semiconductor treatment media and the transfer media; and b) maintaining a continuous supply and removal of these mediums.

25 De installatie bevat typisch verder de opslag-opstellingen van de verschillende semiconductor behandelings- en transfermediums.The installation typically further comprises the storage arrangements of the various semiconductor treatment and transfer mediums.

In een gunstige alternatieve uitvoering ervan bevat deze middelen ten behoeve van in het uitgangsgedeelte ervan het verwijderen van de . opvolgende metalen folie-gedeeltes vanaf de opvolgende semiconductor .In a favorable alternative embodiment thereof, it comprises means for the purpose of removing it in its starting part. subsequent metal foil portions from the subsequent semiconductor.

30 substraat-gedeeltes als een tijdelijke semiconductor onderlaag ervan.30 substrate portions as a temporary semiconductor substrate thereof.

Daarbij bevat deze installatie in een volgende gunstge uitvoering ervan aan de uitgangszijde van de tunnel-opstelling middelen ten behoeve van via een reinigings-inrichting verplaatsen van deze folie naar een opslagrol ervoor.In addition, in a subsequent favorable embodiment thereof, this installation comprises means on the exit side of the tunnel arrangement for displacing this foil via a cleaning device to a storage roll before it.

35 In een volgende gunstige uitvoering van deze installatie daarbij de opname van een rol-opstelling aan de ingangszijde van de tunnel-opstelling ten behoeve van het opnieuw invoeren van de gereinigde folie daarin.In a further favorable embodiment of this installation, the inclusion of a roll arrangement on the entrance side of the tunnel arrangement for the purpose of re-introducing the cleaned film therein.

Daarbij daartoe achter zulk een onder deze tunnel-opstelling opgencraen 3 reinigings-inrichting voor deze metalen folie de opname van een inrichting ten behoeve van het daarin op de bovenwand ervan opbouwen van een pm hoge laag vloeibaar geleidingsmedium voor een gemakkelijke verplaatsing ervan door deze tunnel-opstelling.To this end, behind such a cleaning device for this metal foil 3 arranged under this tunnel arrangement, the accommodation of a device for constructing therein a µm high layer of liquid conducting medium on the upper wall thereof for easy movement thereof through this tunnel structure. setup.

5 Verder fungeert in een gunstige uitvoering van deze installatie zulk een folie als een ononderbroken metalen semiconductor substraat draag/ transferband ten behoeve van het nabij de ingang van de daarin opgenomen tunnel-opstelling opbrengen erop van opvolgende typisch kunststoffen folie-gedeeltes, welke daartoe afkomstig zijn van een folie-opslagrol.Furthermore, in a favorable embodiment of this installation, such a film functions as a continuous metal semiconductor substrate carrier / transfer band for the purpose of applying onto subsequent entrance of the tunnel arrangement contained therein on subsequent typical plastic film sections which originate for this purpose. of a foil storage roll.

10 Daarbij is in een gunstige uitvoering van deze band de bovenwand tenminste ter plaatse van het centrale semiconductor behandelings-gedeelte ervan verdiept ten behoeve van het daarin opnemen van deze opvolgende folie-gedeeltes en wordt daarbij typisch een mechanisch contact onderhouden tussen deze opvolgend band- en folie-gedeeltes.In a favorable embodiment of this belt, the top wall is deepened at least at the location of the central semiconductor treatment part thereof for the purpose of accommodating these successive film parts therein and a mechanical contact is typically maintained between these successive belt and film sections. foil sections.

15 Bij de bestaande semiconductor installaties onder toepassing van opslag van semiconductor wafers in cassettes en transfer ervan naar en vanaf opvolgende semiconductor behandelings-modules ten behoeve van de vervaardiging van semiconductor chips tenminste mede de reeds deze bijgaande Nedelandse Octrooi-aanvrage No. 1 omschreven nadelen ervan.With the existing semiconductor installations using storage of semiconductor wafers in cassettes and transfer thereof to and from subsequent semiconductor treatment modules for the manufacture of semiconductor chips, at least in part also the Dutch Patent Application no. Disadvantages described in 1.

20 Verder daarbij aanvullend het navolgende:20 In addition, the following:

Bij toepassing daarin van de combinatie van een nagenoeg cilindrische wafer als semiconductor substraat en opvolgende semiconductor substraat behandelings-modules, waarin geen mogelijke lineaire verplaatsing ervan erdoorheen, moet daarbij ten behoeve van de bewerkstelliging van een 25 semiconductor substraat, waaruit door deling ervan het verkrijgen van semiconductor chips, aldus de noodzakelijke opbouw van een aantal opvolgende semiconductor lagen, welke uitsluitend in hoogterichting op elkaar liggen met tussengelegen typisch di-electrische semiconductor lagen, bevattende metalen semiconductor doorverbindingen voor deze 30 semiconductor lagen.When applying a combination of a substantially cylindrical wafer as a semiconductor substrate and subsequent semiconductor substrate treatment modules, in which no possible linear displacement thereof, it is necessary for the purpose of effecting a semiconductor substrate from which, by dividing it, obtaining semiconductor chips, thus the necessary construction of a number of successive semiconductor layers, which are only superimposed in height direction with intermediate typical dielectric semiconductor layers, containing metal semiconductor interconnections for these semiconductor layers.

Daarbij geen enkele mogelijkheid van zulke semiconductor lagen cm opvolgend in een lineaire richting naast elkaar te liggen.In addition, there is no possibility of such semiconductor layers being placed next to each other in a linear direction.

Aldus de noodzaak van een uiterst dure en complexe semiconductor installatie, bevattende een zeer groot aantal semiconductor behandelings-35 modules.Thus the need for an extremely expensive and complex semiconductor installation, containing a very large number of semiconductor treatment modules.

Daarbij bij toepassing van een vijftal op elkaar gelegen semiconductor lage, met voor elke typisch nagenoeg ronde laag een benodigde individuele belichtingspatroon-opbreng-inrichting en een groot aantal 4 individuele semiconductor benandelings-inrichtingen en bevattende eveneens een aanzienlijke omvang ervan.In addition, using five superimposed semiconductor low, with an individual exposure pattern application device required for each typically substantially round layer and a large number of 4 individual semiconductor treatment devices and also containing a considerable size thereof.

Zulks tevens voor de daarbij tussengelegen viertal semiconductor verbindingslagen met eveneens tenminste mede de noodzakelijke toepassing 5 van een groot aantal van zulke semiconductor inrichtingen.This is also the case for the intervening four semiconductor connection layers with at least also the necessary application of a large number of such semiconductor devices.

Aldus mede daardoor de noodzaak van een groot aantal benodigde semiconductor reinigings-behandelingen ten behoeve van de bewerkstelliging van een totaal semiconductor behandelings-proces voor zulk een semiconductor substraat met typisch een daarbij benodigde de-10 electrische onderlaag ervan voor het daaruit verkrijgen vah zulke chips.Thus partly because of this the necessity of a large number of semiconductor cleaning treatments required for the realization of a total semiconductor treatment process for such a semiconductor substrate with typically a de-electric underlayment needed therefor for obtaining such chips therefrom.

Daarbij mede door de steeds verdere verkleining van de breedte van de metalen semiconductor verbindingen in zulk een semiconductor laag, nu reeds typisch minder dan 40 nanometer, een steeds verdere.bemoeilijking van het totale semiconductor behandelings-proces en zulks tevens door 15 het uiterst nauwkeurig boven elkaar moeten liggen van deze opvolgende semiconductor lagen met de tussengelegen metalen doorverbindingen.In addition, partly due to the ever-further reduction of the width of the metal semiconductor connections in such a semiconductor layer, now typically less than 40 nanometers, an ever further complication of the total semiconductor treatment process and this also due to the extremely accurate above must lie apart from these subsequent semiconductor layers with the intermediate metal interconnections.

In deze nieuwe semiconductor installatie nu echter mede door deze nanometer grote lijnbreedtes de mogelijke ideale bewerkstelliging van opvolgende semiconductor substraat-gedeeltes> bevattende slechts één 20 semiconductor laag en waaruit in een inrichting achter zulk een semiconductor tunnel-opstelling door deling ervan het verkrijgen van zulke semiconductor chips met slechts deze enkele semiconductor laag en toch daarbij een toelaatbare cmvang ervan.In this new semiconductor installation, however, partly due to these nanometer wide line widths, the possible ideal realization of successive semiconductor substrate sections> comprising only one semiconductor layer and from which in such a device behind such a semiconductor tunnel arrangement by dividing it, obtaining such semiconductor chips with only this single semiconductor layer and yet with a permissible size.

In zulk een semiconductor installatie verder tevens de 25 mogelijke toepassing van meerdere van de middelen en werkwijzen van de semiconductor inrichtingen, welke door de aanvrager zijn ontschreven in de gelijktijdig hiermede ingediende Nederlandse Octrooi-aanvragen.In such a semiconductor installation furthermore also the possible application of several of the means and methods of the semiconductor devices, which have been described by the applicant in the Dutch Patent applications filed with this.

Verder in deze semiconductor installatie de mogelijke toepassing van alle reeds algemeen gebruikt wordende semiconductor behandelingen voor 30 wafers in semiconductor modules, ook welke reeds zijn omschreven inFurthermore in this semiconductor installation the possible application of all already commonly used semiconductor treatments for 30 wafers in semiconductor modules, also those already described in

Octrooien, indien daarin de vermelding in de tekst en Conclusies van het navolgende: a) een individuele seniconductor wafer of - substraat; en/of b) een al dan niet individuele semiconductor processincr-module.Patents, if therein the mention in the text and Conclusions of the following: a) an individual seniconductor wafer or substrate; and / or b) an individual or non-individual semiconductor processincr module.

35 Verder zijn de in deze Octrooi-aanvrage ontschreven middelen en werkwijzen tevens toepasbaar in de semiconductor installaties of delen ervan, welke zijn omschreven in de gelijktijdig door de aanvrager ingediende Nederlandse Octrooi-aanvragen.Furthermore, the means and methods described in this Patent Application are also applicable to the semiconductor installations or parts thereof, which are described in the Dutch Patent Applications submitted simultaneously by the applicant.

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Figuur 1 toont schematisch de semiconductor installatie volgens de uitvinding in een zijaanzicht ervan.Figure 1 schematically shows the semiconductor installation according to the invention in a side view thereof.

Figuur 2 toont een doorsnede over de lijn 2-2 van de in deze installatie opgencmen semiconductor tunnel-opstelling ter plaatse van het 5 ingangsgedeelte ervan.Figure 2 shows a section along the line 2-2 of the semiconductor tunnel arrangement included in this installation at the entrance portion thereof.

Figuur 3 toont een langsdoorsnede van het begingedeelte van deze semiconductor tunnel ter plaatse van het centrale semiconductor behandelings-gedeelte ervan.Figure 3 shows a longitudinal section of the initial part of this semiconductor tunnel at the location of the central semiconductor treatment part thereof.

Figuur 3 toont daarbij sterk vergroot een tunneldoortocht-gedeelte ter 10 plaatse van de in de bovenwand van het boventunnelblok opgencmen stripvormige transducer-opstelling.Figure 3 shows a greatly enlarged tunnel passage section at the location of the strip-shaped transducer arrangement included in the upper wall of the upper tunnel block.

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Figuur 3 toont daarbij sterk vergroot de tunneldoorgang achter deze transducer-opstelling.Figure 3 shows the tunnel passage behind this transducer arrangement greatly enlarged.

Figuur 4 toont sterk vergroot een langsdoorsnede-gedeelte van de 15 tunneldoorgang ter plaatse van een toe- en afvoergroef in het ondertunnelblok voor vloeibaar transfer/geleidingsmedium.Figure 4 shows a greatly enlarged longitudinal sectional portion of the tunnel passage at the location of a supply and discharge groove in the sub-tunnel block for liquid transfer / conducting medium.

Figuur 5 toont schematisch de semiconductor installatie in een alternatieve uitvoering ervan en waarbij daarin in een inrichting achter de tunnel-opstelling het met behulp van een rol-opstelling plaatsvinden 20 van scheiding van de opvolgende semiconductor substraat-gedeeltes van de opvolgende folie-gedeeltes onder daarbij opslag van deze opvolgend folie-' gedeeltes in een folie-opslagrol-opstelling.Figure 5 shows schematically the semiconductor installation in an alternative embodiment thereof and in which a separation of the successive semiconductor substrate sections from the successive foil sections takes place therein in a device behind the tunnel arrangement storage of these successive film portions in a film storage roll arrangement.

Figuur 6 toont een alternatieve uitvoering van de installatie volgens de Figuur 5 en waarbij daarin ter plaatse van de ingang van deze 25 semiconductor tunnel-opstelling de opname van een rol-opstelling ten behoeve van het mede daarmede bewerkstelligen van een ononderbroken metalen semiconductor substraat draag/transferband en waarbij op deze band het opbrengen van opvolgende typisch kunststoffen folie-gedeeltes, welke afkomstig zijn van een in deze installatie opgencmen folie-opslagrol.Figure 6 shows an alternative embodiment of the installation according to Figure 5 and in which there, at the location of the entrance of this semiconductor tunnel arrangement, supports the incorporation of a roll arrangement for the purpose of thereby bringing about a continuous metal semiconductor substrate / transfer belt and wherein on this belt the application of subsequent typical plastic film sections, which originate from a film storage roller included in this installation.

30 Figuur 7 toont een dwarsdoorsnede van een band-uitvoering met een verdiept centraal gedeelte van de bovenwand ervan ten behoeve van het daarin opnemen van de opvolgende folie-gedeeltes.Figure 7 shows a cross-section of a tape version with a recessed central portion of its upper wall for the purpose of receiving the subsequent foil portions therein.

Figuur 8 toont een gedeelte van een alternatieve uitvoering van de semiconductor installatie met daarin het ononderbroken door de tunnel-35 opstelling ervan verplaatsen van een ononderbroken folie draag/ transferband met daarop een tweetal opvolgende aaneengesloten foliën.Figure 8 shows a part of an alternative embodiment of the semiconductor installation with therein continuously moving through the tunnel arrangement an uninterrupted foil carrier / transfer belt with two consecutive contiguous foils thereon.

Figuur 9 toont een gedeeltelijk bovenaanzicht van de opvolgende, door de inrichting achter de uitgang van de tunnel-opstelling verplaatsende 6Figure 9 shows a partial plan view of the successive 6 moving 6 through the device behind the exit of the tunnel arrangement

Figuur 10 toont sterk vergroot een bovenaanzicht van de na deling van deze opvolgende semiconductor substraat-gedeeltes bewerkstelligde semiconductor chip, bevattende daarbij typisch slechts één semiconductor bovenlaag.Figure 10 shows a highly enlarged top plan view of the semiconductor chip effected after division of these successive semiconductor substrate portions, typically comprising only one semiconductor top layer.

5 Figuren 11^ tot en met 11 tonen de in deze semiconductor opstelling na de bewerkstelliging van de opvolgende typisch sub um wijde uitsparingen (crevices) in de di-electrische bovenlaag van de opvolgende erdoorheen verplaatsende semiconductor substraat-gedeeltes in opvolgende phasen het 10 reinigen ervan.Figures 11 ^ to 11 show the cleaning in this semiconductor arrangement after the creation of the subsequent typically sub-wide recesses (crevices) in the dielectric top layer of the subsequent semiconductor substrate portions moving therethrough in subsequent phases .

Figuur 12 toont daarbij daartoe de toepassing van een typisch hoog-frequente trilconditie van tenminste mede deze opvolgende semiconductor substraat-gedeeltes met behulp van een roterende nokkenas in het ondertunnelblok.Figure 12 shows the application of a typical high-frequency vibration condition of at least these successive semiconductor substrate sections with the aid of a rotating camshaft in the sub-tunnel block.

15 Figuren 13 en sterk vergroot de Figuren 14 en 15^ t/m EFigures 13 and greatly enlarged Figures 14 and 15 to E inclusive

tonen met behulp van een roterende slijpas, welke is opgenomen in het boventunnelblok ter plaatse van het centrale gedeelte ervan het verwijderen van het resterende gedeelte van de benodigde um hoge harde di-electrische belichtingslaag 20 op de di-electrische bovenlaag van de opvolgende eronderlangs verplaatsende semiconductor substraat-gedeeltes.with the aid of a rotary grinding, which is incorporated in the upper tunnel block at the location of the central portion thereof, show the removal of the remaining portion of the required um high hard dielectric exposure layer 20 on the dielectric upper layer of the subsequent semiconductor moving along it substrate portions.

Figuur 16 en sterk vergroot Figuur 17 tonen het met behulp van een roterende nokkenas, bevattende multi in dwarsrichting ervan ter plaatse van het centrale semiconductor behandelings-25 gedeelte uitstrekkende scherpkantige um grote nokken, het verwijderen van deze resterende belichtingslaag.Figure 16 and greatly enlarged Figure 17 shows the removal of this remaining exposure layer with the aid of a rotating camshaft containing multi transversely extending transversely at the location of the central semiconductor treatment section.

Figuur 18, sterk vergroot Figuur 19 en zeer sterk vergroot Figuren 20A t/m E tonen na het in een voorgaand tunnel-gedeelte met metaal-deeltjes vullen van deze semiconductor 30 en het vervolgens plaatsvinden van een oven- en afkoel behandeling ervan verwijderen van tenminste de extra opgebrachte sub-um hoge metaallaag.Figure 18, greatly enlarged Figure 19 and greatly enlarged Figures 20A to E show, after filling this semiconductor 30 in a previous tunnel section with metal particles and then following an oven and cooling treatment, removing at least the extra applied sub-um high metal layer.

Figuur 21 toont een semiconductor chip met slechts één enkele di-electrische semiconductor schakelings-laag, typisch 35 bevattende met elkaar verbonden nanometer brede, met metaal gevulde semiconductor groeven onder het bewerkstelligd zijn van een .électtische schakeling met electrische aansluit-gedeeltes .Fig. 21 shows a semiconductor chip with only a single dielectric semiconductor circuit layer, typically comprising interconnected nanometer-wide, metal-filled semiconductor grooves while having an electrical circuit with electrical connection portions.

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Figuur 22 toont een semiconductor chip met een tweetal boven elkaar gelegen di-electrische schakelings-lagen, elk bevattende zulke met metaal gevulde groeven en welke met behulp van tenminste nagenoeg verticale, met metaal gevulde 5 groeven met elkaar verbonden zijn onder de vorming van met elkaar verbonden electrische schakeling-tgedeeltes.Figure 22 shows a semiconductor chip with two superimposed dielectric circuit layers, each containing such metal-filled grooves and which are connected to each other with the help of at least substantially vertical, metal-filled grooves to form one another connected electrical circuit portions.

Figuur 23 toont een semiconductor chip met een kunststof, typisch teflon onderlaag met zulk een daarop verankerde di-electrische bovenlaag.Figure 23 shows a semiconductor chip with a plastic, typically Teflon bottom layer with such a dielectric top layer anchored thereon.

10 Figuur 24 toont daarbij een semiconductor chip met een relatief dikke kunststof onderlaag, welke ononderbroken wordt aangevoerd vanuit een folie-opslagrol nabij de ingang van de semiconductor tunnel-opstelling.Figure 24 shows a semiconductor chip with a relatively thick plastic bottom layer, which is supplied continuously from a foil storage roller near the entrance of the semiconductor tunnel arrangement.

Figuur 25 toont een semiconductor chip met een kunststof 15 onderlaag en een tweetal boven elkaar gelegen di-electrische schakelings-lagen, bevattende met elkaar verbonden electrische schakeling-sgedeeltes.Figure 25 shows a semiconductor chip with a plastic bottom layer and two superimposed dielectric circuit layers, containing mutually connected electrical circuit portions.

Figuur 26 toont een semiconductor chip, waarbij op een kunststof onderlaag het verankerd opgebracht zijn van een 20 metalen tussenlaag met daarop verankerd zulk een di-electrische bovenlaag.Figure 26 shows a semiconductor chip in which an anchored metal layer is provided on a plastic substrate with such a dielectric top layer anchored thereon.

Figuur 27 toont de semiconductor chip volgens de Figuur 26, waarbij op deze metalen tussenlaag een tweetal boven elkaar gelegen di-electrische lagen, elk bevattende zulke met metaal 25 gevulde groeven en welke lagen eveneens electrisch met elkaar zijn gekoppeld.Figure 27 shows the semiconductor chip according to Figure 26, wherein on this metal intermediate layer two dielectric layers are located one above the other, each containing such grooves filled with metal 25 and which layers are also electrically coupled to each other.

Figuur 28 toont een semiconductor chip met een metalen onderlaag en zulk een daarop verankerde di-electrische schakelings-laag, bevattende zulk een electrisch schakelings-30 laag.Figure 28 shows a semiconductor chip with a metal bottom layer and such a dielectric circuit layer anchored thereon, containing such an electrical circuit layer.

Figuur 29 toont een semiconductor chip met een metalen onderlaag en een tweetal verankerde boven elkaar gelegen di-electrische lagen, elk eveneens bevattende zulke met metaal gevulde semiconductor groeven en welke eveneens 35 electrisch met elkaar zijn gekoppeld.Figure 29 shows a semiconductor chip with a metal bottom layer and two anchored superimposed dielectric layers, each also containing such metal-filled semiconductor grooves and which are also electrically coupled to each other.

Figuur 30 toont een semiconductor chip met een paperen onderlaag en zulk een daarop verankerde di-electrische bovenlaag.Figure 30 shows a semiconductor chip with a paper base layer and such a dielectric top layer anchored thereon.

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Figuur 31 toont een semiconductor chip met een papieren onderlaag, een daarop verankerde metalen tussenlaag en de daarop verankerde di-electrische bovenlaag.Figure 31 shows a semiconductor chip with a paper substrate, an intermediate metal layer anchored thereon and the dielectric upper layer anchored thereon.

Figuur 32 toont een semiconductor chip met een metalen 5 onderlaag, een kunstof tussenlaag en zulk een bovenlaag.Figure 32 shows a semiconductor chip with a metal lower layer, a plastic intermediate layer and such an upper layer.

De uitvinding zal hieronder nader woden uiteengezet aan de hand van een aantal in de Figuren weergegeven uitvoeringsvoorbeelden van de installatie-opbouw volgens de uitvinding.The invention will be explained in more detail below with reference to a number of exemplary embodiments of the installation structure according to the invention shown in the Figures.

Figuur 1 toont schematisch de semiconductor installatie volgens de 10 uitvinding in een zijaanzicht ervan.Figure 1 schematically shows the semiconductor installation according to the invention in a side view thereof.

Zulk een semiconductor installatie bestaat daarbij typisch in hoofdzaak uit een zich in de lengterichting ervan uitstrekkende semiconductor subtraat transfer/behandelingstunnel-opstelling 12, bevattende een boventunnelblok 14, een ondertunnelblok 16 en de ertussen opgencmen 15 centrale tunneldoortocht 18, Figuren 2 en 3.Such a semiconductor installation typically consists essentially of a longitudinal semiconductor substrate transfer / treatment tunnel arrangement 12, comprising an upper tunnel block 14, a lower tunnel block 16 and the central tunnel passage 18 interposed between them, Figures 2 and 3.

In zulk een semiconductor installatie nabij de ingangszijde 20 van deze semiconductor tunnel-opstelling 12 de opname van een opslagrol-opstelling 22 ten behoeve van tijdens de werking ervan de ononderbroken toevoer van een zeer lange folie met typische slechts een minder dan 0,1 mm dikte 20 ervan en bevattende een typisch tenminste nagenoeg evenwijdige opstaande zijwand-gedeeltes 26 en 28.In such a semiconductor installation near the entrance side 20 of this semiconductor tunnel arrangement 12 the inclusion of a storage roller arrangement 22 for the continuous supply of a very long film during its operation with a thickness typically less than 0.1 mm thick 20 and comprising a typically substantially parallel upright sidewall portions 26 and 28.

lijens de werking van zulk een semiconductor installatie vindt daarbij een ononderbroken lineaire verplaatsing van deze folie 24 door deze tunneldoortocht 18 plaats.During the operation of such a semiconductor installation, continuous linear displacement of this foil 24 through this tunnel passage 18 takes place.

25 Daarbij in de opvolgende secties van het centrale boven-semiconductor behandelings-gedeelte van de tunneldoorocht 18 het ononderbroken plaatsvinden van opbouw van tenminste één semiconductor laag op de bovenzijde van deze folie onder de bewerkstelliging van opvolgende, zich ononderbroken onderlangs dit bcven-behandelingsgedeelte van deze 30 tuuneldoortocht verplaatsende semiconductor substraat-gedeeltes,In the subsequent sections of the central upper semiconductor treatment section of the tunnel passageway 18, the uninterrupted occurrence of the construction of at least one semiconductor layer on the upper side of this film under the effect of successive, uninterrupted downstream of this upper treatment section of this 30 garden passage moving semiconductor substrate sections,

Figuur 3 toont een langsdoorsnede van het begingedeelte nan deze semiconductor tunnel 12 ter plaatse van het centrale semiconductor behandelings-gedeelte ervan.Figure 3 shows a longitudinal section of the initial part of this semiconductor tunnel 12 at the location of the central semiconductor treatment part thereof.

Ten behoeve van verankering van de eerste semiconductor laag op deze 35 folie 24 nabij de ingang 20 van deze tunneldoorgang 18 vindt achter de stripvormige slotsectie 30 en zulks via de stripvormige toevoersectie 32 in het boventunnelblok 14 ter plaatse van 'het bovenspleet-gedeelte van de tunneldoorgang 18 het ononderbroken toevoeren van de combinatie van 9 laagkokend vloeibaar draagmedium 36 en deeltjes vloeibaar hechtmedium 38 plaats en waarbij met behulp van een in de onderwand van dit tunnelblok opgenomen stripvormige transducer-opstelling 40, welke tevens fungeert als warmtebron, het in het eronder gelegen gedeelte van deze boven-5 behandelingsspleetgedeelte plaatsvinden van verdamping van dit laagkokende vloeibare draagmedium 36, met daarbij neerslag van deze deeltjes vloeibaar hechtmedium 38 op de opvolgende eronderlangs verplaatsende folie-gedeeltes,onder de vorming van een gelijkmatige jam hoge film van deze vloeibare hechtsubstantie 38 en waarbij in een daarop 10 volgende stripvormige afvoersectie 42 in dit boventunnelblok het plaatsvinden van afvoer van dit verdampte medium.For the purpose of anchoring the first semiconductor layer on this foil 24 near the entrance 20 of this tunnel passage 18, behind the strip-shaped lock section 30 and this via the strip-shaped supply section 32 in the upper tunnel block 14 at the location of the upper slit portion of the tunnel passage 18 the uninterrupted supply of the combination of 9 low-boiling liquid carrier medium 36 and particles of liquid adhesive medium 38 takes place and wherein, with the aid of a strip-shaped transducer arrangement 40 which is included in the bottom wall of this tunnel block, which also acts as a heat source, the part situated below of this above treatment slit portion evaporation of this low-boiling liquid carrier medium 36, with deposition of these particles of liquid adhesive medium 38 on the subsequent film portions moving therebetween, to form a uniform jam high film of this liquid adhesive substance 38 and wherein in a subsequent 10 sts rip-shaped discharge section 42 in this upper tunnel block the discharge of this evaporated medium.

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Daarbij toont Figuur 3 sterk vergroot een gedeelte van deze bovenspleet 34 ander deze transducer-opstelling 40, met daarin reeds het plaatsvinden van neerslag van deeltjes vloeibare hechtsubstantie 38 op de opvolgende,Figure 3 shows a highly enlarged part of this upper slit 34 and this transducer arrangement 40 already showing the deposition of particles of liquid adhesive substance 38 on the subsequent one.

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15 eronderlangs folie-gedeeltes 24 en Figuur 3 een gedeelte van deze bovenspleet 34 achter deze afvoersectie 42 en waarbij ter plaatse zulk een opgebouwde pm hoge laag van dit hechtmedium 38 op deze opvolgende, eronderlangs verplaatsende folie-gedeeltes 24.15 below, foil sections 24 and Figure 3 show a portion of this upper slit 34 behind this discharge section 42, and in which such a built-up high layer of this adhesive medium 38 on these successive foil sections 24 moving below it.

Daarbij, zoals is aangegeven in de Figuren 3 en sterk vergroot 20 Figuur 4, teminste mede plaatselijk in tenminste de bovenwand van het ondertunnelblok 16 de opname van, gezien in de verplaatsingsrichting van deze opvolgende ononderbroken erbovenlangs verplaatsende semiconductor substraat-gedeeltes 44, opvolgende, in de lengterichting van deze tunnel uitstrekkende groeven 46 met aan de ingangszijde ervan aansluiting erop 25 van een stripvormige toevoersectie 48 voor typisch hoogkokend vloeibaar transfer/geleidingsmedium 50, met aan de uitgangszijde ervan de aansluiting erop van een stripvormige afvoersectie 54 ten behoeve van het continue onderhouden van opvolgende stromen ervan langs de onderwand van deze opvolgende folie-gedeeltes onder het daarbij gelijktijdig onderhouden 30 van een jam hoge film ervan in tenminste mede de tussengelegen onderpleet-sectie 58 en ondersteunen van de verplaatsing van deze opvolgende semiconductor substraat-gedeeltes door de tunneldoorgang 18.Thereby, as indicated in Figs. 3 and greatly enlarged, Fig. 4, at least partly locally in at least the upper wall of the sub-tunnel block 16, the incorporation of, viewed in the direction of movement of these successive continuous semiconductor substrate portions 44 passing along it, into, grooves 46 extending in the longitudinal direction of this tunnel with connection thereto at its inlet 25 of a strip-shaped supply section 48 for typical high-boiling liquid transfer / conducting medium 50, with at its output side the connection thereto of a strip-shaped discharge section 54 for the continuous maintenance of subsequent flows thereof along the bottom wall of these successive film sections, while simultaneously maintaining a jam-high film thereof in at least the intermediate lower gap section 58 and supporting the movement of these successive semiconductor substrate sections through the tunnel passage 18.

Daarbij, zoals verder is aangegeven in de Figuur 4, in de opvolgende secties van het centrale boven-semiconductorbehandelingsgedeelte 60 van 35 deze tunneldoortocht het ononderbroken opbouwen van de opvolgende semiconductor lagen op de bovenzijde van deze folie 24 onder de bewerkstelliging van deze opvolgende, zich ononderbroken onderlangs dit centrale boven-semiconductor behandelingsspleetgedeelte 34 verplaatsende 10 semiconductor substraat-gedeeltes 44.In addition, as further indicated in Figure 4, in the subsequent sections of the central top semiconductor treatment section 60 of this tunnel passage, the continuous building up of the subsequent semiconductor layers on the top of this foil 24 while effecting these successive, continuous moving semiconductor substrate portions 44 along this central upper semiconductor treatment slit portion 34.

In de Figuur 5 is een schematisch zijaanzicht van de alternatieve semiconductor installatie 10' aangegeven, waarbij daarin tijdens de werking ervan in de inrichting 62 het ononderbroken plaatsvinden van 5 scheiding van de opvolgende gedeeltes van de metalen folie 24' van de daarop in de semiconductor tunnel-opstelling 12' opgebrachte opvolgende semiconductor substraat-gedeeltes 44'.Figure 5 shows a schematic side view of the alternative semiconductor installation 10 ', in which, during its operation in the device 62, uninterrupted separation of the successive parts of the metal foil 24' from the one in the semiconductor tunnel thereon takes place. arrangement 12 'applied successive semiconductor substrate portions 44'.

Deze opvolgende folie-gedeeltes zijn daarbij afkomstig uit de folie-opslagrol 22'.These successive film portions are thereby taken from the film storage roll 22 '.

10 Ten behoeve van de bewerkstelliging van zulk een scheiding daarbij het voorafgaand in het begingedeelte van de tunnel-opstelling 12' op deze opvolgende folie-gedeeltes aangebracht zijn van een pm hoge film zeer hoogkokend vloeibaar medium, typisch gallium, (¾} tenminste het centrale semiconductor behandelings-gedeelte ervan.For the purpose of effecting such a separation, prior to the initial portion of the tunnel arrangement 12 'having been applied to these successive film portions of a µm high-film very high-boiling liquid medium, typically gallium, (¾} at least the central semiconductor treatment part thereof.

15 Daarbij via mede de rol-opstelling 64 het verplaatsen van deze opvolgende folie-gedeeltes naar de reinigings-inrichting 66 ten behoeve van het daarin ononderbroken plaatsvinden van reiniging van in het bijzonder het boven-oppervlak ervan.Thereby moving these successive film portions to the cleaning device 66 for the purpose of continuous cleaning of, in particular, the upper surface thereof, via the roller arrangement 64.

Vervolgens vindt daarbij in de rol-opstelling 68 opslag van deze 20 opvolgende folie-gedeeltes plaats.Subsequently, in the roll arrangement 68, these 20 successive foil sections are stored.

Daarbij fungeert deze rol-opstelling 68 tevens ten behoeve van het daarbij uitoefenen van een trekkracht op deze opvolgende folie-gedeeltes.This roller arrangement 68 also functions for the purpose of exerting a tensile force on these successive film sections.

In de aangepaste inrichting 70 vindt daarbij na reiniging van de opvolgende, daarin ononderbroken toegevoerde semiconductor substraat-25 gedeeltes 44' deling ervan in semiconductor chips 72 plaats.In the adapted device 70, after cleaning of the subsequent semiconductor substrate portions continuously supplied therein, division thereof into semiconductor chips 72 takes place.

De in tenminste de Figuren 1, 2 en 5 aangegeven folie 24 bestaat typisch uit kunststof of een metaal en waarbij aldus de semiconductor onderlaag van de in de tunnel-opstelling 12 van deze semiconductor installatie 10 bewerkstelligde opvolgende semiconductoe substraat-30 gedeeltes 44 en daarmede eveneens zulk een semiconductor chip 72 tenminste mede uit zulk een kunststof of metaal bestaat.The foil 24 shown at least in Figs. 1, 2 and 5 typically consists of plastic or a metal and the semiconductor substrate of the successive semiconductor substrate portions 30 effected in the tunnel arrangement 12 of this semiconductor installation 10 and thus also such a semiconductor chip 72 at least partly comprises such a plastic or metal.

Figuur 6 toont de semiconductor installatie 10", waarbij in de ingang van de tunnel-opstelling 12" de rol-opstelling 78 ten behoeve van het wederom invoeren van de in de inrichting 66" gereinigde opvolgende 35 gedeeltes van de folie 24"in deze semiconductor tunnel-opstelling 12", met het typisch fungeren ervan als een ononderbroken semiconductor draag/transferband.Figure 6 shows the semiconductor installation 10 ", wherein at the entrance of the tunnel arrangement 12" the roll arrangement 78 for the re-introduction of the successive portions of the film 24 "cleaned in the device 66" into this semiconductor tunnel arrangement 12 ", with it typically functioning as a continuous semiconductor carrier / transfer band.

in de inrichting 80 vindt daartoe na deze reinigings-inrichting 66" 11 daarbij het mede plaatsvinden van het opbouwen van een pm hoge film tijdelijke vloeibare hechtsubstantie 82 op de opvolgende, zich ononderbroken erdoorheen verplaatsende, mede daartoe in geringe mate dikkere metalen band 76.for this purpose, in device 80, after this cleaning device 66 "11, co-mounting of a pm high film of temporary liquid adhesive substance 82 takes place on the subsequent metal strip 76 which moves continuously through it, partly for that purpose, slightly thicker metal strip 76.

Daarbij in een gunstige werking van deze installatie 10" vindt een 5 ononderbroken toevoer van opvolgende folie-gedeeltes74 vanaf de folie-opslagrol 22" plaats ten behoeve van het in het in het ingangs-gedeelte 20" van deze tunnel-opstelling 12" opbrengen ervan op deze band 76 met daarbij deze tussengelegen um hoge laag tijdelijke hechtsubstantie 82.Thereby, in a favorable operation of this installation 10 ", a continuous supply of successive film portions74 from the film storage roller 22" takes place for the purpose of inserting it into the input portion 20 "of this tunnel arrangement 12". on this belt 76 with this intermediate um high layer temporary adhesive substance 82.

Verder met behulp van deze hechtsubstantie het in voldoende mate 10 zodanig tijdelijk verankeren op de opvolgende bandgédeeltes 7 6 van de in deze tunnel-opstelling 12" bewerkstelligde opvolgende semiconductor substraat-gedeeltes 44", dat in de inrichting 62" achter deze tunnel-opstelling het mogelijk plaatsvinden van scheiding van deze opvolgende semiconductor substraat-gedeeltes van de opvolgende bandgedeeltes, 15 Figuur 7 toont een gunstige uitvoering van deze semiconductor substraat draag/transferband 76, waarbij de bovenwand ter plaatse van het centrale semiconductor behandelings-gedeelte 60" in geringe mate verdiept is ten behoeve van het daarin ophouwen van zulke opvolgende semiconductor substraat-gedeeltes 44'", met typisch de 20 opvolgende folie-gedeeltes 74 als een definitieve semiconductor onderlaag ervan.Furthermore, with the aid of this adhesive substance, anchoring to a sufficient extent 10 sufficiently on the subsequent band sections 7 6 of the successive semiconductor substrate portions 44 "realized in this tunnel arrangement 12, that in the device 62" behind this tunnel arrangement possible separation of these successive semiconductor substrate parts from the successive band parts, Figure 7 shows a favorable embodiment of this semiconductor substrate carrier / transfer band 76, wherein the top wall slightly deepened at the location of the central semiconductor treatment part 60 " for the purpose of carving therein such successive semiconductor substrate portions 44 '", with typically the successive foil portions 74 as a final semiconductor substrate thereof.

Daarbij zijn de op het verdiepte centrale gedeelte 84 van deze band 76 opgebrachte opvolgende folie-gedeeltes 74 als definitieve semiconductor onderlaag van zulke opvolgende semiconductor substraat-25 gedeeltes in voldoende mate daarop verankerd door een mechanisch contact van deze daartoe optimaal vlakke opvolgende folie-gedeeltes met de eveneens optimaal vlakke verdiepte bovenwand-gedeeltes van deze bandThe successive foil portions 74 applied to the deepened central portion 84 of this belt 76 are then anchored sufficiently as a definitive semiconductor substrate of such successive semiconductor substrate portions by mechanical contact of these successively flat successive foil portions with the also optimally flat sunken upper wall sections of this belt

Zulks mede door daarbij de toepassing van zulk een semiconductor substraat draag/transferband 76, dat deze met tenminste één opstaande 30 zijwand 86 correspondeert met een vlakke opstaande zijwand 88 van deThis is partly due to the use of such a semiconductor substrate carrier / transfer band 76 that it corresponds to at least one upright side wall 86 with a flat upright side wall 88 of the

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tunneldoorgang 18tunnel passage 18

Verder, dat daarbij mede daartoe de ópstaande zijwand 90 van dit . verdiepte gedeelte 84 van deze band 76 t welke correspondeert met de opstaande zijwand 86 ervan, eveneens in voldoende mate in zowel de lengte-35 als hoogterichting vlak is en zulks tevens voor de daarmede corresponderende opstaande zijwand 26 van de opvolgende folie-gedeeltes 74.Furthermore, this also includes the upright side wall 90 of this. recessed portion 84 of this belt 76 t, which corresponds to its upright side wall 86, is also sufficiently flat in both the longitudinal and height directions, and this is also the case for the corresponding upright side wall 26 of the subsequent foil sections 74.

Verder, dat daarbij tijdens de warmte-behandeling van een bovenlaag-gedeelte van de opvolgende semiconductor substraat-gedeeltes 44', zoals is 12 anschreven in de toekomstige Nederlandse Octrooi-aanvragen van de aanvrager, het mede beletten van een ontoelaatbare vervorming in dwarsrichting ervan.Furthermore, during the heat treatment of an upper layer portion of the subsequent semiconductor substrate portions 44 ', as described in the future Dutch Patent Applications of the applicant, thereby also preventing an inadmissible transverse deformation thereof.

Daarbij daartoe in opvolgende semiconductor warmte-behandelingssecties 5 in de onderwand van het boventunnelblok 14 de opname van een ym grote electrische verwarmingsdraad, met het daarbij gedurende een zeer korte tijd opwarmen van slechts een (sub) jam hoge opgebrachte semiconductor substantie, zoals een di-electrische substantie en typisch in de lengterichting opzij ervan een afkoel-inrichting.To this end, in subsequent semiconductor heat treatment sections 5 in the lower wall of the upper tunnel block 14, the inclusion of a ym large electric heating wire, with the heating of only a (sub) jam high applied semiconductor substance, such as a diode, for a very short time. electrical substance and typically a cooling device in the longitudinal direction aside thereof.

10 Verder mede daartoe het in een gunstige werkwijze in deze tunnel-opstelling 12 opbouwen van slechts één semiconductor bovenlaag op typisch een kunststof folie 24, waardoor tenminste mede het navolgende: a) een geringe toelaatbare vervorming ervan tijdens zulk een oven- 15 behandelingsproces; en b) een geringe toelaatbare uitrekking ervan in de lengterichting van de tunneldoorgang 18 tijdens de lineaire verplaatsing ervan erdoorheen, cmdat daarbij in een stripvormige tunnelsectie slechts één enkel belichtingsproces benodigd is.Partly for this purpose also in a favorable method in this tunnel arrangement 12 is to build up only one semiconductor top layer on typically a plastic film 24, whereby at least partly the following: a) a low permissible deformation thereof during such an oven treatment process; and b) a slight permissible extension thereof in the longitudinal direction of the tunnel passage 18 during its linear displacement therethrough, since only a single exposure process is required in a strip-shaped tunnel section.

20 Daarbij tijdens de werking van deze tunnel-opstelling met een ononderbroken verplaatsing van zulk een combinatie van ononderbroken band 76 en typisch ononderbroken opvolgende semiconductor substraat-gedeeltes 44 net mede daarbij onderhouden van een nagenoeg evenwijdige positie van zulk een opstaande zijwand van deze folie 24 met de 25 daarmede corresponderende ópstaande zijwand 8 8 van de tunneldoorgang 18 met behulp van opvolgende stromen gasvormig medium langs de . bovenwand ervan en het daarbij onderhouden van het navolgende: a) geleiding van deze band 76 langs zulk een opstaande zijwand van de tunneldoorgang 18 ; en 30 b) aanliggen van een opstaande zijwand 9 2 van de opvolgende folie-gedeeltes 74 tegen de opstaande zijwand 90 van dit verdiepte bovenwand-gedeelte 84 van deze band 76.In addition, during the operation of this tunnel arrangement with an uninterrupted displacement of such a combination of uninterrupted belt 76 and typically uninterrupted successive semiconductor substrate portions 44, while also maintaining a substantially parallel position of such an upright side wall of this foil 24 with the corresponding side wall 8 of the tunnel passage 18 with the aid of successive flows of gaseous medium along the. its upper wall and thereby maintaining the following: a) guiding of this belt 76 along such an upright side wall of the tunnel passage 18; and b) abutting an upright side wall 9 of the subsequent foil sections 74 against the upright side wall 90 of this recessed upper wall section 84 of this band 76.

Figuur 8 toont voor de semiconductor installatie 10 middelen ten behoeve van het bewerkstelligen van tijdens de werking ervan daarin in 35 het ingangsgedeelte 20 van de daarin opgencmen semiconductor tunnel- opstelling 12 het aansluiten op de achterzijde 94 van de reeds erdoorheen verplaatste folie 24 van de voorzijde 96 van de volgende folie 24.Figure 8 shows, for the semiconductor installation 10, means for effecting, during its operation, therein in the entrance portion 20 of the semiconductor tunnel arrangement 12 accommodated therein, connecting to the rear side 94 of the foil 24 already moved therethrough from the front side 96 of the following foil 24.

Daartoe bevatten deze foliën 24 aan de voorzijde ervan de vlakke 13 opstaande zijwand 96 en aan de achterzijde de vlakke opstaande zijwand 98 en welke tenminste nagenoeg evenwijdig zijn.To this end, these foils 24 comprise, at the front thereof, the flat upright side wall 96 and at the rear side the flat upright side wall 98 and which are at least substantially parallel.

In een gunstige uitvoering van zulk een in de opslagrol 68 opgeslagen folie 24 is daarbij de lengte ervan groter dan die van deze tunnel-5 opstelling 12, typisch meer dan 20 meter en zelfs mogelijk 5000 meter ten behoeve van gedurende circa 2 maanden het onderhouden van een continue ononderbroken verplaatsing ervan erdoorheen en met een daarin gelijktijdig ononderbroken plaatsvinden van de opvolgende semiconductor behandelingen.In a favorable embodiment of such a foil 24 stored in the storage roller 68, the length thereof is thereby greater than that of this tunnel arrangement 12, typically more than 20 meters and even possibly 5000 meters for the purpose of maintaining for approximately 2 months. a continuous uninterrupted movement thereof through and with the subsequent continuous semiconductor treatments taking place simultaneously therein.

Zulks bij een verplaatsingssnelheid van deze folie van 2 irm/seconde.This at a displacement speed of this film of 2 irm / second.

10 Aldus tenminste een circa 3 uren tijdsduur, voordat een volgende folie moet worden ingebracht.Thus at least a duration of approximately 3 hours, before a next film must be introduced.

Daarbij bevat tunnel-ingangsgedeelte 20"in een gunstige uitvoering aan de bovenzijde ervan een open centraal gedeelte 100 ten behoeve van inspectie van zulk een bewerkstelligde critische aansluiting van deze 15 opvolgende foliën en waarbij ter plaatse van de beide dwarsuiteinden gg van de tunneldoorgang 18 het plaatsvinden van geleiding van de ingebrachte volgende folie.Tunnel entrance part 20 ", in a favorable embodiment, comprises an open central part 100 at the top thereof for the purpose of inspecting such a achieved critical connection of these successive films and where the two transverse ends gg of the tunnel passage 18 take place of guiding the introduced next film.

Daarbij typisch tenminste mede met behulp van opvolgende stromen gasvormig medium langs deze nieuwe folie in de richting van de voorgaande 20 folie met het onderhouden van een hogere snelheid van het voorgedeelte van deze folie dan die van de voorgaande folie totdat zulk een aansluiting heeft plaats gevonden.Typically at least partly with the aid of successive flows of gaseous medium along this new film in the direction of the previous film while maintaining a higher speed of the front part of this film than that of the previous film until such a connection has been made.

Zulk een folie-toevoersysteem is gedetailleerd aangegeven en omschreven in de .binnenkort nog in te dienen corresponderende 'Octrooi- 25 aanvrage door de aanvrager.Such a foil feed system is detailed and described in the corresponding patent application to be filed by the applicant shortly.

De reinigings-inrichting 66"bevat daarbij verder zodanige middelen, dat daarin tevens het plaatsvinden van verwijdering van een eventueel op de op de daarbij toegepaste tand 24" terechtgekomen substantie. Figuur 6.The cleaning device 66 "further comprises means such that it also takes place the removal of any substance that has fallen on the tooth 24" used therein. Figure 6.

Zulk een geringe tunnellengte is ook mogelijk bij toepassing van 30 opvolgende semiconductor substraatgedeeltes 44 met typisch slechts één semiconductor bovenlaag en waaruit in de inrichting 62 door deling ervan de bewerkstelliging van semiconductor chips 72 met slechts zulk een enkele semiconductor opbouw ervan. Figuren 1 en 2.Such a small tunnel length is also possible when 30 consecutive semiconductor substrate portions 44 are typically used with typically only one semiconductor top layer and from which, by dividing it, the realization of semiconductor chips 72 having only such a single semiconductor structure in the device 62. Figures 1 and 2.

Zulk een mogelijke enkele semiconductorlaag in plaats van een aantal 35 boven elkaar gelegen semiconductor lagen, zoals tot op heden algemeen gebruikelijk is in de bestaande semiconductor industrie onder toepassing van nagenoeg cilindrische semiconductor wafers en tenminste mede individuele semiconductor behandelings-modules met verticale metalen 14 doorverbindingen ertussen.Such a possible single semiconductor layer instead of a number of superimposed semiconductor layers, as is generally used to date in the existing semiconductor industry using substantially cylindrical semiconductor wafers and at least partly individual semiconductor treatment modules with vertical metals 14 interconnections between them .

In een alternatieve mogelijke uitvoering van zulk een folie- 24 is de lengte ervan minder dan die van deze semiconductor tunnel-opstelling 12, waardoor een daarbij noodzakelijke veelvuldige inbrenging van zulk een 5 volgende folie, typisch daarbij binnen 2 uur.In an alternative possible embodiment of such a foil 24, its length is less than that of this semiconductor tunnel arrangement 12, thereby requiring a frequent introduction of such a subsequent foil, typically within 2 hours.

Verder kan zulk een inbrengen van het begin van de volgende folie zover handmatig worden ondersteund totdat aansluiting ervan op deze voorgaande folie heeft plaats gevonden en waarbij vervolgens tijdens de verdere verplaatsing van deze combinatie van foliën door deze stranen 10 gasvormig medium zulk een aansluiting blijft gehandhaafd.Furthermore, such insertion of the beginning of the next film can be supported manually until it has been connected to this previous film and, subsequently, such a connection is maintained during the further displacement of this combination of films through these tapes gaseous medium.

Door zulk een in het ingangsgedeelte van de tunnel-opstelling aansluiten van de volgende folie op de voorgaande folie vindt daarbij aldus mogelijk tenminste mede een ononderbroken toe- en afvoer van semiconductor behandelingsmedium naar en vanaf de opvolgende stripvormige 15 boven semiconductor behandelingsspleetsecties van deze semiconductor tunnel-opstelling plaats.By connecting the following foil to the preceding foil in the entrance part of the tunnel arrangement, there is thus at least possibly an uninterrupted supply and discharge of semiconductor treatment medium to and from the subsequent strip-shaped above semiconductor treatment gap sections of this semiconductor tunnel tunnel. set up place.

Aldus een geheel nieuwe semiconductor transfer/behandelings-technologie onder de bewerkstelliging van semiconductor chips met daarbij de toepassing van elke mogelijke substantie voor zulk een semiconductor 20 folie of een ccmbinatie van substanties ervoor, zoals mede is aangegeven en cmschreven in de· vele, toekomstig in te dienen Octrooiaanvragen door de aanvrager, betreffende mede zulke semiconductor chips.Thus a completely new semiconductor transfer / treatment technology under the realization of semiconductor chips with the application of any possible substance for such a semiconductor foil or a combination of substances before it, as indicated and described in the many, future Patent applications to be filed by the applicant, including such semiconductor chips.

Zulks mede door de in de volgende Octrooi-aanvragen aangegeven en cmschreven aanvullende middelen en werkwijzen ten behoeve van tenminste 25 mede een hoog effectieve en bijzondere opbouw van tenminste één semiconductor laag op zulk een folie als tenminste tijdelijke semiconductor onderlaag van de in deze semiconductor installatie bewerkstelligde opvolgende semiconductor substraat-gedeeltes, waaruit door deling ervan het verkrijgen van zulke semiconductor chips.This is partly due to the additional means and methods indicated and described in the following Patent Applications for at least a highly effective and special construction of at least one semiconductor layer on such a film as at least a temporary semiconductor lower layer of the layer realized in this semiconductor installation. successive semiconductor substrate portions, from which by dividing it, obtaining such semiconductor chips.

30 In de Figuur 9 is verder nog een gedeeltelijk bovenaanzicht aangegeven van de opvolgende, zich ononderbroken door de inrichting 62 achter de tunnel-uitgang 52, Figuur 1, verplaatsende opvolgende semiconductor substraat-gedeeltes 44.Figure 9 furthermore shows a partial top view of the successive semiconductor substrate portions 44 moving continuously through the device 62 behind the tunnel output 52, Figure 1.

Daarbij bestaat zulk een semiconductor substraat-gedeelte 44 uit een 35 aantal opvolgende, in dwarsrichting naast elkaar gelegen semiconductor substraataecties, waaruit door deling ervan in deze inrichting de bewerkstelliging van semiconductor chips 72, typisch bevattende slechts één enkele semiconductor bovenlaag op een typisch kunststof folie 24.In addition, such a semiconductor substrate portion 44 consists of a number of consecutive transverse semiconductor substrate sections, from which by dividing it into this device the realization of semiconductor chips 72, typically containing only a single semiconductor top layer on a typical plastic film 24 .

15 als definitieve semiconductor onderlaag ervan.15 as its final semiconductor substrate.

Figuur 10 toont sterk vergroot een bovenaanzicht van de bewerkstelligde semiconductor chip 72, bevattende op deze typisch kunststof onderlaag de semiconductor bovenlaag 102 in samengehechte toestand als vervanger 5 voor de bestaande semiconductor chips met een aantal boven elkaai gelegen semiconductor lagen met tussengelegen metalen semiconductor doorverbindingen.Figure 10 shows greatly enlarged a top view of the semiconductor chip 72 realized, comprising on this typical plastic bottom layer the semiconductor top layer 102 in the bonded state as a replacement 5 for the existing semiconductor chips with a number of semiconductor layers with intermediate metal semiconductor interconnections.

Daarbij is typisch de afmeting van zulk een semiconductor chip 72 in dwarsrichting circa gelijk aan die in de lengterichting ervan.In this case, the dimension of such a semiconductor chip 72 is approximately equal in the transverse direction to that in its longitudinal direction.

10 Verder voor zulk een semiconductor chip elk mogelijk aantal electrische aansluitingen 134 en elke mogelijke positie ervan.Furthermore, for such a semiconductor chip, any possible number of electrical connections 134 and any possible position thereof.

Verder voor de semiconductor grondlaag van zulk een chip elke mogelijke combinatie van boven elkaar gelegen pm hoge lagen, zoals onder andere een di-electrische onderlaag, een metalen tussenlaag en een di-electrische 15 bovenlaag.Furthermore, for the semiconductor base layer of such a chip, any possible combination of superimposed pm high layers, such as, inter alia, a dielectric lower layer, a metal intermediate layer and a dielectric upper layer.

Verder de mogelijke toepassing van een aantal boven elkaar gelegen semiconductor lagen met metalen doorverbindingen ertussen.Furthermore, the possible application of a number of superimposed semiconductor layers with metal interconnections between them.

Verder bevat deze semiconductor installatie zodanige middelen, dat daarbij met behulp van een in het boventunnelblok van de daarin opgenomen 20 semiconductor tunnel-cpstelling stripvormige belichtingspatxoon- opbrenginrichting het plaatsvinden van het op de opvolgende eronder langs verplaatsende semiconductor substraat-gedeeltes opbrengen van een stripvormig' belichtingspatroon.This semiconductor installation further comprises means such that, with the aid of a strip-shaped exposure pattern applying device arranged in the upper tunnel block of the semiconductor tunnel arrangement therein, the application of a strip-shaped exposure pattern moving along the subsequent semiconductor substrate sections below .

Daarbij daartoe in de beide dwarsuiteinden van zulk een semiconductor 25 band of - folie het aangebracht zijn van opvolgende uitsparingen 104, Figuur 8 ' ten behoeve van het met behulp van deze band of folie mede-verplaatsen van deze belichtingspatroon -opbrenginrichting met de opgebrachte opvolgende semiconductor substraat-gedeeltes tijdens het belichtingsproces.To this end, the two transverse ends of such a semiconductor belt or film are provided with successive recesses 104, Figure 8 'for the purpose of co-displacing this illumination pattern-applying device with the applied successive semiconductor with the aid of this belt or film. substrate portions during the exposure process.

30 In zulk een semiconductor installatie 10,met de daarin opgenonen semiconductor substraat transfer/behandelings-tunnelopstelling 12, tenminste mede de toepassing van een folie-opslagrol 22 nabij de ingang ervan ten behoeve van tijdens de werking ervan het plaatsvinden van een ononderbroken verplaatsing van de opvolgende folie-gedeeltes erdoorheen 35 en vindt daarbij in de achter de uitgang 52 van deze tunnel- opstelling opgenctnen inrichting 62 tenminste mede door deling van de opvolgende, daarin ononderbroken toegevoerde semiconductor substraat-gedeeltes de bewerkstelliging van semiconductor chips 72 met tenminste 16 mede een semiconductor laag-opbouw.In such a semiconductor installation 10, with the semiconductor substrate transfer / treatment tunnel arrangement 12 accommodated therein, at least also the use of a foil storage roller 22 near its entrance for the purpose of continuous movement of the successive foil sections therethrough and thereby finds device 62 accommodated behind the exit 52 of this tunnel arrangement, at least partly by dividing the subsequent semiconductor substrate sections continuously supplied therein, the realization of semiconductor chips 72 with at least 16 partly a semiconductor low build.

Daarbij door het in deze tunnel-opstelling bewerkstelligd zijn van slechts één enkele semiconductor laag, welke tevens fungeert als semiconductor bovenlaag van de opvolgende, ononderbroken erdoorheen 5 verplaatsende semiconductor substraat-gedeeltes, tenminste mede de navolgende semiconductor laag-opbouwen van zulke, daaruit verkregen semiconductor chips: a) de combinatie van een kunststoffen onderlaag en een di-electrische bovenlaag; of 10 b) de combinatie van een kunststoffen onderlaag, een metalen tussenlaag en een di-electrische bovenlaag; of c) de combinatie van een metalen onderlaag en een di-electrische bovenlaag; of d) uitsluitend een di-electrische bovenlaag; of 15 e) de combinatie van een di-electrische aiderlaag, een metalen tussenlaag ai een di-electrische bovenlaag.In addition, due to the fact that in this tunnel arrangement only a single semiconductor layer is effected, which also functions as a semiconductor top layer of the successive, continuously moving semiconductor substrate sections through it, at least also the following semiconductor layer structures of such semiconductor obtained therefrom chips: a) the combination of a plastic bottom layer and a dielectric top layer; or b) the combination of a plastic bottom layer, a metal intermediate layer and a dielectric top layer; or c) the combination of a metal bottom layer and a dielectric top layer; or d) only a dielectric top layer; or e) the combination of a dielectric aider layer, a metal intermediate layer ai dielectric top layer.

Indien echter in zulk een tunnel-opstelling de bewerkstelliging van een aantal boven elkaar gelegen primaire semiconductor lagen met secundaire tussenlagen, bevattende een aantal metalen doorverbindingen 20 tussen deze primaire semiconductor lagen, daarbij eveneens het mogelijk plaatsvinden van de onder a), b), C), d) ene) vermelde semiconductor laag-opbouwen van zulke, daaruit verkregen semiconductor chips.However, if in such a tunnel arrangement the realization of a number of superimposed primary semiconductor layers with secondary intermediate layers, comprising a number of metal interconnections between these primary semiconductor layers, thereby also the possible occurrence of the sub a), b), C ), d) a specified semiconductor layer build-up of such semiconductor chips obtained therefrom.

indien in zulk een semiconductor tunnel-opstelling uitsluitend de toepassing van een ononderbroken metalen semiconductor substraatdraag/ 25 band 76 met de rol-opstellingen 64 en 78 nabij de uit- en ingang ervan, Figuur 6, en met daarin de bewerkstelliging van opvolgende semiconductor substraat-gedeeltes met slechte een enkele semiconductor laag, welke daarbij tevens fungeert als semiconductor bovenlaag ervan, daarbij echter slechts de semiconductor laag-opbouwen van de uit zulk een 30 inrichting verkregen semiconductor chips,welke zijn vermeld aider d) en e).if in such a semiconductor tunnel arrangement only the use of a continuous metal semiconductor substrate support / belt 76 with the roll arrangements 64 and 78 near the exit and entrance thereof, Figure 6, and including the realization of successive semiconductor substrate portions with only a single semiconductor layer, which thereby also functions as its semiconductor top layer, but only building up the semiconductor layer of the semiconductor chips obtained from such a device, which are mentioned aider d) and e).

Als daarbij in zulk een tunnel-opstelling de bewerkstelliging van opvolgende semiconductor substraat-gedeeltes, bevattende een aantal boven elkaar gelegen primaire semiconductor lagen met secundaire semiconductor tussenlagen, waarin de opname van een aantal metalen 35 doorverbindingen tussen deze primaire lagen, daarbij eveneens voor de uit deze inrichting verkregen semiconductor chips slechts deze onder d) en e) vermelde semiconductor laag-opbouwen.As in such a tunnel arrangement, the realization of successive semiconductor substrate sections, comprising a number of superimposed primary semiconductor layers with secondary semiconductor intermediate layers, in which the incorporation of a number of metal interconnections between these primary layers, also for the semiconductor chips obtained in this device only build up the semiconductor layer mentioned under d) and e).

Indien echter de toepassing van de combinatie van zulk een 17 ononderbroken semiconductor substraat draag/transferband en de daarop ononderbroken vanaf een opslagrol-opstelling erop opgebrachte opvolgende saai conductor folie-gedeeltes, daarbij wederom tenminste mede de onder a), b), c), d) en e) vermelde mogelijke semiconductor laag-opbouwen_ van de 5 daaruit verkregen semiconductor chips.However, if the application of the combination of such a continuous semiconductor substrate carrier / transfer belt and the subsequent boring conductor foil portions applied thereto from a storage roll arrangement thereon, again including at least the points a), b), c), d) and e) the possible semiconductor layer construction of the 5 semiconductor chips obtained therefrom.

Zulk een semiconductor kunststof-folie of -laag bevat een voldoend hoge smelttemperatuur en di-electrische waarde ervan ten behoeve van het fungeren ervan als tenminste semiconductor onderlaag van de opvolgende, in deze semiconductor tunnel-opstelling bewerkstelligde semiconductor 10 substraat-gedeeltes en vervolgens in een daarachter opgenomen inrichting tenminste mede door deling ervan het verkrijgen van semiconductor chips met zulk een semiconductor onderlaag ervan.Such a semiconductor plastic film or layer contains a sufficiently high melting temperature and dielectric value thereof for the purpose of functioning as at least a semiconductor bottom layer of the successive semiconductor substrate 10 arranged in this semiconductor tunnel arrangement and subsequently in a device included behind it at least partly by dividing it by obtaining semiconductor chips with such a semiconductor bottom layer thereof.

Verder is tevens een tenminste mede papieren folie in een daartoe geschikte uitvoering en samenstelling ervan toepasbaar voor tenminste 15 zulk een semiconductor onderlaag van de opvolgende, in deze tunnel-opstelling bewerkstelligde semiconductor substraat-gedeeltes en in de daarachter opgenamen inrichting door deling ervan opvolgende semiconductor chips.Furthermore, an at least co-paper film in a suitable embodiment and composition thereof can also be used for at least one such semiconductor substrate of the subsequent semiconductor substrate portions effected in this tunnel arrangement and in the device accommodated behind it by division thereof subsequent semiconductor chips .

Verder is elke afmeting van zulk een typisch rechthoekige 20 semiconductor chip met zulk een tenminste mede papieren onderlaag-gedeelte in zowel de lengte- en dwarsrichting ervan mogelijk.Furthermore, any dimension of such a typically rectangular semiconductor chip with such an at least co-paper backing layer portion is possible in both its longitudinal and transverse directions.

In een gunstige uitvoering van zulk een kunststoffen - of papieren folie vindt daarbij in een inrichting, welke al dan niet is opgencmen in deze semiconductor installatie, op tenminste het centrale 25 semiconductor behandelings-gedeelte ervan het opbrengen van een pm hoge laag di-electrische substantie plaats ten behoeve van het in de tunnel-opstelling ervan bewerkstelligen van met metaal gevulde nanometer grote uitsparingen in de bovenwand van de daarin bewerkstelligde opvolgende semiconductor substraat-gedeeltes en 30 vervolgens door tenminste mede deling ervan in de erachter opgenomen inrichting het verkrijgen van semiconductor chips met zulk een semiconductor onder- en bovenlaag ervan.In a favorable embodiment of such a plastic or paper foil, in a device which may or may not be included in this semiconductor installation, the application of a pm high layer of dielectric substance on at least the central semiconductor treatment part thereof for the purpose of effecting, in the tunnel arrangement thereof, metal-filled nanometer-sized recesses in the upper wall of the successive semiconductor substrate portions effected therein and subsequently obtaining semiconductor chips with, at least, their communication in the subsequent device such a semiconductor top and bottom layer.

Verder wordt in deze tunnel-opstelling met behulp van de opvolgende folie/band-gedeeltes in combinatie met opvolgende stromen slotmedium in 35 de beide dwarsuiteinden van de tunneldoorgang een mediumslot onderhouden voor het vermijden van het terechtkomen van het behandelings-medium vanuit de primaire bovenspleet in de secundaire onderspleet en medium vanuit deze onderspleet in deze bovenspleet.Furthermore, in this tunnel arrangement, a medium slot is maintained in the two transverse ends of the tunnel passage with the aid of the subsequent foil / tape sections in combination with successive streams of lock medium to prevent the treatment medium from ending up from the primary top slit in the secondary under-gap and medium from this under-gap in this top-gap.

1818

Na het in de semiconductor tunnel-opstelling bewerkstelligen van zulke typisch (sub) ;im grote groeven (crevices) in de boventopography 108 van de di-electrische bovenlaag van de opvolgende semiconductor substraat-5 gedeeltes 44 onder toepassing van een belichte zeer harde semiconductor bovenlaag 110 het in opvolgende stripvormige boven-behandelingsspleetsecties 34 plaatsvinden van opvolgende phasen van een totaal reinigings-proces van deze groeven 106, Figuren 11A t/"1 11F_ 10 Daarbij de toepassing van een stripvormige drukwand 112 als deel van de bovenwand van het ondertunnelblok 16, welke met behulp van de roterende nokkenas 114 in dit blok typisch hoog-frequent trillend op en neer wordt bewogen en zulks onder typisch van deze opvolgende semiconductor substraat-15 gedeeltes 44, Figuur 12.After effecting such typical (sub) im grooves in the top topography 108 of the dielectric top layer of the successive semiconductor substrate portions 44 in the semiconductor tunnel arrangement using an exposed very hard semiconductor top layer 110 the occurrence of successive phases of a total cleaning process of these grooves 106 in successive strip-shaped upper treatment slit sections 34, Figs. 11A to "11F" 10 The use of a strip-shaped pressure wall 112 as part of the upper wall of the sub-tunnel block 16, which is moved up and down typically high-frequency vibrating up and down with the aid of the rotating camshaft 114 in this block, and this under typical of these successive semiconductor substrate sections 44, FIG. 12.

Daarbij in de Figuren 11 A en 11B in opvolgende spleet-secties met behulp van typisch vloeibaar reinigingsmedium 116 het plaatsvinden van de beginphase van dit reinigings-proces.In Figures 11A and 11B, the starting phase of this cleaning process takes place in successive slit sections with the aid of typical liquid cleaning medium 116.

Daarbij opvolgend een opwaartse compressieslag, met het 20 instuwen van dit reinigingsmedium en in de daarop volgende neerwaartse expansieslag het uit deze groeven 106 uitstuwen van de combinatie van deeltjes van dit vloeibare reinigingsmedium en de combinatie van nog aanwezige deeltjes typisch di-electrische substantie 118 en deeltjes etsmedium 120, 25 totdat zulk een reinigings-proces heeft plaats gevonden, Figuren llc en llD,Thereafter an upward compression stroke, with the pushing in of this cleaning medium and in the subsequent downward expansion stroke, ejecting from these grooves 106 the combination of particles of this liquid cleaning medium and the combination of particles still present, typically dielectric substance 118 and particles etching medium 120, 25 until such a cleaning process has taken place, Figures 11c and 11D,

Vervolgens in t-ypisch een aantal daarop volgende boven-spleetsectie 34 het met behulp van gasvormig medium 122, typisch N2, verwijderen van dit vloeibare medium uit deze 30 groeven 106, Figuren 11^ en llF.Subsequently, in a number of subsequent upper slit section 34, with the aid of gaseous medium 122, typically N 2, removing this liquid medium from these grooves 106, Figures 11 and 11F.

Vervolgens in een volgend stripvormig tunnel-gedeelte, Figuur 13, het ononderbroken wegslijpen van op de di-electrische bovenlaag 124 opgebrachte resterende harde di-electrische bovenlaag-gedeeltes 110 met behulp van een 35 in het boventunnel blok 14 opgenomen roterende slijp-as 126 en waarbij zulk een slijp-proces sterk vergroot in Figuur 14 en zeer sterk vergroot in de Figuren 15A t/m E.Next, in a subsequent strip-shaped tunnel section, Figure 13, the continuous grinding of residual hard dielectric upper layer sections 110 applied to the dielectric upper layer 124 with the aid of a rotating grinding shaft 126 included in the upper tunnel block 14 and wherein such a grinding process is greatly enlarged in Figure 14 and greatly enlarged in Figures 15A to E.

Daarbij met behulp van de stripvormige drukwand in het 19 ondertunnelblok 16 een opwaartse aandrukkracht van de opvolgende semiconductor substraat-gedeeltes 44 tegen deze slijp-as .Thereby, with the aid of the strip-shaped pressure wall in the sub-tunnel block 16, an upward pressing force of the subsequent semiconductor substrate portions 44 against this grinding axis.

Zulk een verwijdering van deze harde di-electrische laag 5 110 is ook mogelijk met behulp van de roterende nokkenas- opstelling 130, bevattende een zeer groot aantal um hoge scherpkantige nokken 132, Figuren 16 en 17.Such a removal of this hard dielectric layer 110 is also possible with the aid of the rotating camshaft arrangement 130, comprising a very large number of high-angled cams 132, Figures 16 and 17.

Na het opbrengen van de combinatie van laag-kokend vloeibaar draagmedium 36 en metaal-deeltjes 134 en daar bij 10 tenminste mede vullen van deze groeven 106, met de opbouw van tevens een .um hoge laag ervan op de bovenwand van de opvolgende, eronderlangs verplaatsende semiconductor substraat-gedeeltes 44 onder toepassing van zulk een boven-transduceropstelling 40 in het boventunnelblok 14, 15 Figuur 3, ten behoeve van het verdampen van dit vloeibare draagmedium en in een daarop volgend oven-behandeling van deze opgebrachte laag en een daarop volgend afkoel-proces met behulp van mede een tim groot electrisch verwarmings-in het boventunnelblok, vindt in een volgend tunnel-20 gedeelte typisch met . behulp van zulk een roterende slijp-as 126 het wegslijpen van tenminste het teveel opgebrachte metaal als een (sub) um hoge metaallaag 128 plaats.After applying the combination of low-boiling liquid carrier medium 36 and metal particles 134 and at least thereby filling these grooves 106, with the construction of also a very high layer thereof on the upper wall of the successive, moving below it semiconductor substrate portions 44 using such an upper transducer arrangement 40 in the upper tunnel block 14, Figure 3, for the purpose of vaporizing this liquid carrier medium and in a subsequent oven treatment of this applied layer and a subsequent cooling down. process with the aid of a large electrical heating in the upper tunnel block, typically takes place in a subsequent tunnel section. by means of such a rotary grinding shaft 126, grinding away of at least the excessly applied metal takes place as a (sub) um high metal layer 128.

Zulk een wegslijpen van deze metaallaag is aangegeven in de Figuren 18 en 19 en zeer sterk vergroot in de opvolgende 25 Figuren 20^ t/|n E.Such a grinding of this metal layer is indicated in Figures 18 and 19 and greatly increased in the subsequent Figures 20 ^ t / n E.

Als alternatief het mogelijk allereerst in een tunnel-gedeelte vullen van deze groeven in de combinatie van de di-electrische bovenlaag en de um hoge harde di-electrische toplaag met metaal en vervolgens in een volgend tunnel-30 gedeelte het met behulp van zulk een roterende slijp-as wegslijpen van de combinatie van deze harde di-electrische belichtingslaag en de opgebrachte um hoge metaallaag.Alternatively, it is possible first of all to fill these grooves in a tunnel section in the combination of the dielectric top layer and the um high hard dielectric top layer with metal and then in a subsequent tunnel section it with the aid of such a rotating grinding axis grinding away the combination of this hard dielectric exposure layer and the applied um high metal layer.

Figuur 21 toont een semiconductor chip 72^.welke in de inrichting 70, Figuur 5, of de inrichting 62, Figuur 1, 35 achter zulk een semiconductor tunnel-opstelling 12 door deling van de daarin ononderbroken toegevoerde opvolgende semiconductor substraat-gedeeltes 44 verkregen wordt.Fig. 21 shows a semiconductor chip 72 which is obtained in the device 70, Fig. 5, or the device 62, Fig. 1, 35 behind such a semiconductor tunnel arrangement 12 by dividing the successively supplied successive semiconductor substrate portions 44 therein. .

Deze chip is zodanig uitgevoerd, dat deze slechts één 20 di-electrische schakelings-laag 124 bevat en waarbij in de boventopography 108 ervan de opname van multi, met metaal gevulde typisch nanometer brede semiconductor groeven 106, welke met elkaar zijn doorverbonden onder de bewerkstelliging 5 van een electrische schakeling met daarop enige electrische aansluit-gedeeltes 134.This chip is designed in such a way that it contains only one dielectric circuit layer 124, and in its top topography 108 the incorporation of multi, metal-filled, typically nanometer-wide semiconductor grooves 106 interconnected under operation 5 of an electrical circuit with some electrical connection parts 134 thereon.

Figuur 22 toont een semiconductor chip 72*1, waarbij deze een tweetal boven elkaar gelegen en met elkaar verankerde di-electrische schakelings-lagen 124 en 124' bevat.Figure 22 shows a semiconductor chip 72 * 1, in which it comprises two superimposed and anchored dielectric circuit layers 124 and 124 '.

10 Daarbij in de boventopography 108 van elke laag eveneens de opname van zulke multi, met metaal gevulde typisch nanometer brede groeven 106 en 106', waarin de bewerkstelliging van een electrisch schakelings-gedeelte en waar bij deze groeven plaatselijk met tenminste nagenoeg 15 verticale doorverbindings-groeven 136 met elkaar zijn verbonden en de bovenste electrische schakeling electrische aansluit-gedeeltes 134 bevat.In addition, in the top topography 108 of each layer, there is also the inclusion of such multi-metal-filled, typically nanometer-wide grooves 106 and 106 ', in which the realization of an electrical circuit portion and where at these grooves locally with at least substantially vertical interconnection grooves 136 are connected to each other and the upper electrical circuit includes electrical connection portions 134.

Figuur 23 toont de semiconductor chip 72^, waarbij deze bestaat uit een tenminste in voldoende mate hitte-bestendige 20 kunststof, typisch teflon, onderlaag 138, met daarop zulk een in deze tunnel-opstelling opgebrachte en daarmede al dan niet met een (sub) jim hoge tussenlaag hechtsubstantie verankerde di-electrische bovenlaag 124, bevattende wederom in de boven-topography 108 ervan de met metaal gevulde 25 groeven 106 met daarop de electrische aansluitingen 134.Figure 23 shows the semiconductor chip 72, consisting of an at least sufficiently heat-resistant plastic, typically Teflon, bottom layer 138, with such a layer applied in this tunnel arrangement and with or without a (sub) In a high interlayer adhesive substance anchored dielectric upper layer 124, again containing in its top-topography 108 the metal-filled grooves 106 with the electrical connections 134 thereon.

Figuur 24 toont de semiconductor chip 72·*·^, waarbij deze bestaat uit een relatief dik kunstof folie-gedeelte 138', welke typisch ononderbroken naar de semiconductor tunnel-opstelling wordt aangevoerd vanaf een folie-opslagrol nabij 30 de ingangszijde ervan, Figuur 1 of 5, of daartoe gebruik is gemaakt van een ononderbroken semiconductor substraat draag/transf er band met een rol-opstelling nabij de in- en uitgang ervan, Figuur 6.Figure 24 shows the semiconductor chip 72, which consists of a relatively thick plastic film portion 138 ', which is typically continuously supplied to the semiconductor tunnel arrangement from a film storage roll near its entrance side, Figure 1 or 5, or use has been made for this purpose of a continuous semiconductor substrate carrier / transfer belt with a roll arrangement near its entrance and exit, Figure 6.

Figuur 25 toont de semiconductor chip 72 V, waarbij deze 35 bestaat uit zulk een kunststof onderlaag 138 met daarop zulk een tweetal in deze tunnel-opstelling opgebrachte boven elkaar gelegen di-electrische schakelings-lagen 124, bevattende eveneens zulke met metaal gevulde groeven 106.Figure 25 shows the semiconductor chip 72 V, wherein it consists of such a plastic bottom layer 138 with such two superimposed dielectric circuit layers 124 arranged in this tunnel arrangement, also containing such metal-filled grooves 106.

2121

Figuur 26 toont de semiconductor chip 72VI, waarbij op een kunststof onderlaag 138 een daarop verankerde metalen tussenlaag 140 met daarop verankerd de di-electrische schakelings-laag 124.Figure 26 shows the semiconductor chip 72VI, wherein on a plastic substrate 138 a metal intermediate layer 140 anchored thereon with the dielectric circuit layer 124 anchored thereon.

5 Figuur 27 toont de semiconductor chip 72^11, waarop op deze combinatie van kunststof onderlaag 138 en metalen tussenlaag 140 een tweetal daarop boven elkaar gelegen schakelings-lagen 124 en 124' met eveneens de met metaal gevulde verbindings-groeven 136 tussen de met metaal 10 gevulde groeven 106 en 106' in de boventopography van deze beide lagen.Figure 27 shows the semiconductor chip 72 ^ 11, on which on this combination of plastic bottom layer 138 and metal intermediate layer 140 two circuit layers 124 and 124 'superimposed thereon, also with the metal-filled connecting grooves 136 between the metal layers 10 filled grooves 106 and 106 'in the top topography of these two layers.

Figuur 28 toont de semiconductor chip 72^111 met een metalen onderlaag 140 en zulk een daarop verankerde schakelings-laag 124, eveneens bevattende de met metaal 15 gevulde groeven 106 in de boventopography 108 ervan en met daarop enige electrische aansluit-gedeeltes 134.Figure 28 shows the semiconductor chip 72 ^ 111 with a metal underlayer 140 and such a circuit layer anchored thereon, also containing the metal-filled grooves 106 in its upper topography 108 and with some electrical connection portions 134 thereon.

Figuur 29 toont de semiconductor chip 72lX met een metalen onderlaag 140 en een tweetal daarop verankerde boven elkaar gelegen di-electrische schakelings-lagen 124 20 en 124', elk bevattende eveneens zulke met metaal gevulde groeven 106 en 106' en de verbindings-groeven 136.Figure 29 shows the semiconductor chip 72x with a metal bottom layer 140 and two superimposed dielectric circuit layers 124 20 and 124 'anchored thereon, each also containing such metal-filled grooves 106 and 106' and the connecting grooves 136 .

Figuur 30 toont de semiconductor chip 72^ met een papieren onderlaag 144 en zulk een daarop verankerde di-electrische schakelings-laag 124, met in de 25 boven-topography 108 ervan wederom de opname van de met metaal gevulde groeven 106 en de daarop aangesloten aansluitingen 134.Figure 30 shows the semiconductor chip 72 with a paper bottom layer 144 and such a dielectric circuit layer anchored thereon, with in its top topography 108 again the incorporation of the metal-filled grooves 106 and the connections connected thereto. 134.

Figuur 31 toont de chip 72^1 met een papieren onderlaag 144 en de daarop verankerde metalen tussenlaag 140 en de 30 daarop verankerde di-electrische schakelings-laag 124.Figure 31 shows the chip 72 ^ 1 with a paper backing layer 144 and the metal intermediate layer 140 anchored thereon and the dielectric circuit layer 124 anchored thereon.

Figuur 32 toont de semiconductor chip 72^11 met een metalen onderlaag ^40, een daarop verankerde kunststof laag 138 en daarop verankerd zulk een di-electrische schakelings-laag 124.Figure 32 shows the semiconductor chip 72 ^ 11 with a metal underlayer ^ 40, a plastic layer 138 anchored thereon and such a dielectric circuit layer 124 anchored thereon.

35 Verder aanvullend en binnen het kader van de uitvinding de typisch mogelijke toepassing van in meerdere van de Conclusies omschreven semiconductor inrichtingen en - werkwijzen.Further additionally and within the scope of the invention, the typical possible application of semiconductor devices and methods described in several of the Claims.

10370631037063

Claims

A semiconductor chip, characterized in that at least the final phase of its manufacture has taken place in "at least partly" a semiconductor installation.

2. A semiconductor chip as claimed in Claim 1, characterized in that such a semiconductor installation is designed for this purpose in such a way that it is effected in a device thereof, viewed in the longitudinal direction of this installation, subsequent semiconductor at least partly realized therein substrate portions.

3. A semiconductor chip as claimed in Claim 2, characterized in that such successive semiconductor substrate portions are achieved exclusively in this semiconductor installation.

4. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that the inclusion of a semiconductor substrate transfer / treatment tunnel arrangement for this purpose in this semiconductor installation.

5. A semiconductor chip as claimed in Claim 4, characterized in that during the operation of this installation in this semiconductor tunnel arrangement, at least substantially uninterrupted location of a uniform linear displacement of said successive semiconductor substrate portions therethrough from at least almost the entrance side to the exit side thereof.

6. A semiconductor chip according to claim 5, characterized in that, for this purpose, these successive semiconductor substrate sections were continuously connected in this semiconductor tunnel arrangement.

7. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that at least partly for such successive semiconductor substrate sections, use is made of foil film continuously supplied therein uninterruptedly via its input via the input thereof. portions with a small thickness thereof as an at least 1037063 temporary semiconductor bottom layer thereof.

8. A semiconductor chip as claimed in Claim 7, characterized in that for this purpose this semiconductor installation, prior to the entrance of this semiconductor tunnel arrangement included therein, comprises a film storage roller, in which the storage of such a film having a thickness thereof is typically less than 0.1 mm and a storage capacity of this storage roll of typically at least 10,000 meters thereof.

9. A semiconductor chip according to claim 4, characterized in that for this purpose a continuous metal semiconductor substrate carrier / transfer belt is used as a temporary semiconductor substrate of these successive moving semiconductor substrate portions for this purpose. , with a roll arrangement 15 near its entrance and exit sides and a drive device for rotating this rear roll and thereby moving the successive tire portions through this tunnel arrangement.

10. Semiconductor chip as claimed in any of the foregoing Claims, characterized in that at least partly for that purpose it is appropriate that at least some of the semiconductor means and methods are indicated and described in the application simultaneously with this Dutch Patent Application by the applicant. Dutch patent application filed for such a semiconductor installation, a patent application for the semiconductor facility in which this semiconductor installation is included, and a strip-shaped feed device for at least the applied semiconductor treatment medium.

11. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that, like the successive semiconductor substrate portions in the output portion of this semiconductor tunnel arrangement, comprising at least partly nanometer-wide metal-filled grooves (crevices) in at least its dielectric top layer, which has an extremely low height, typically less than 0.2 mm.

12. Semiconductor chip according to Claim 11, characterized in that, at least partly for this purpose, in a strip-shaped part of this tunnel arrangement at the location of the central semiconductor treatment part thereof, the uninterrupted effect of a typical nanometer-high layer of particles is achieved. of a semiconductor dielectric substance, whereupon in a subsequent semiconductor treatment section the continuous operation of an oven treatment of successive portions of this layer took place having obtained a fused condition thereof and in a subsequent strip-shaped section have taken place uninterruptedly during a cooling process while processing this layer in its solid state as part of such a semiconductor chip.

13. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that for this purpose, in this semiconductor installation, there have taken place the construction of a number of these nanometer-high layers arranged in successive strip-shaped sections, with typically following each of these applied the continuous occurrence of such a combination of an oven and a subsequent cooling process.

14. Semiconductor chip according to one of the preceding

Claims, characterized in that the height of such an applied dielectric layer is less than 5 µm.

15. A semiconductor chip according to Claim 14, characterized in that the height of such an applied dielectric layer is less than 500 nanometers.

16. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that only after the build-up of a number of such superimposed dielectric layers is applied using the combination of such a strip-shaped medium supply section, vibrating evaporation device and medium discharge section, also such a combination of such a furnace treatment process has taken place while effecting a liquid layer of this dielectric substance and a subsequent cooling process to form a solid condition of such a semiconductor 5 layer.

17. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that it is further designed in such a way that at least partly such a nanometer-high dielectric layer thereof is effected in this semiconductor tunnel arrangement by means of a strip-shaped medium. supply section of its upper tunnel block, the uninterrupted location of the supply of the combination of low-boiling liquid carrier medium and nanometer-sized particles of such a dielectric substance and with the aid of a subsequent strip-shaped vibrating heat source, typically a transducer arrangement , thereby at least partly under the initial part thereof having gradually taken place an ever-increasing evaporation of this low-boiling liquid medium with a simultaneous discharge of this evaporated medium in a subsequent strip-shaped discharge section with the thereby associated of a sufficiently uniform precipitation of these particles on the subsequent semiconductor substrate portions moving continuously underneath it to obtain such a typical nanometer-high layer of particles of this dielectric substance.

18. A semiconductor chip according to Claim 17, characterized in that such a vibrating heat source is a typical at least high-frequency vibrating strip-shaped pressure wall portion of this upper tunnel block and wherein typically with the aid of a rotating camshaft arrangement included in a strip-shaped pressure chamber portion of this block, a rapid downward and subsequent slow upward movement thereof took place.

19. A semiconductor chip as claimed in Claim 17 or 18, characterized in that this semiconductor tunnel arrangement is further designed such that, partly with the aid of this developed vaporous medium in combination with this vibrating strip-shaped heating device, the vibrating pressure wall thereby maintain a contactless condition of such an applied layer of dielectric substance with the upper tunnel block section above and also in this subsequent strip-shaped oven and cooling section.

20. Semiconductor chip according to Claim 19, characterized in that, partly for this purpose, the height of the portion of the upper gap has been maintained, following this strip-shaped medium supply section for this combination of low-boiling liquid carrier medium and particles of dielectric substance which has been larger than the width of this supply section in the longitudinal direction of this tunnel arrangement.

21. Semiconductor chip according to Claim 19, characterized in that for this purpose at least beneath this strip-shaped vibrating heat source are the application of an increasing height of this upper slit portion located below it and this typically up to at least this subsequent medium discharge section.

22. A semiconductor chip according to any one of the preceding Claims, characterized in that, after such a dielectric layer build-up has been achieved in this tunnel arrangement on the subsequent semiconductor substrate portions moving through it in a subsequent strip-shaped tunnel -section have been uninterrupted in its flatness treatment with the aid of the portion of a rotary scraper located in the central section of the upper tunnel block.

23. Semiconductor chip according to Claim 22, characterized in that it is further designed such that, in particular for the lower dielectric layer of these successive semiconductor substrate portions, such a number of repetitions of such a combination of a layer structure and a subsequent scraping process from the highest part thereof, that finally a sufficiently flat condition was achieved.

24. A semiconductor chip as claimed in Claim 23, characterized in that it is furthermore designed in such a way that it is also effected for the uppermost dielectric layer of said successive semiconductor substrate sections by means of such a scraping process. are of such a sufficiently flatness for a subsequent portion of this tunnel arrangement after applying a high exposure layer in subsequent tunnel portions that multi-nanometer wide and deep are achieved therein, metal-filled grooves (crevices) with obtaining a semiconductor electrical circuit layer with electrical connection portions thereon.

25. A semiconductor chip according to any one of the preceding Claims, characterized in that the height of such a single dielectric intermediate layer applied to this successive semiconductor substrate portions is less than 2 µm.

26. A semiconductor chip according to Claim 25, characterized in that the height of such a single applied semiconductor intermediate layer is less than 500 nanometers, typically less than 300 nanometers.

27. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that for such successive semiconductor substrate sections in a part of this tunnel arrangement, a sufficiently flat bottom wall thereof has been achieved using a sub-tunnel block of which the top wall at the location of the central semiconductor treatment section was flat enough in at least the transverse direction thereof.

A semiconductor chip according to Claim 27, characterized in that the upper wall section of the sub-tunnel block was less than 50 nanometers flat for this purpose.

29. A semiconductor chip as claimed in Claim 27 or 28, characterized in that, also for this purpose, there had been no presence of a semiconductor substrate part underneath the entire bottom wall of the successive semiconductor substrate parts moving through it low liquid medium.

30. A semiconductor chip according to claim 29, characterized in that for this purpose the gaseous medium beneath at least a substantial portion thereof was used for this purpose in the successive sub-gap portions of the tunnel passage beneath the successive semiconductor substrate portions have locally maintained mechanical contact of these substrate portions with these ultra-flat central top wall portions of the sub-tunnel block.

31. A semiconductor chip as claimed in Claim 30, characterized in that, to that end, at the location of such a tunnel section, the continuous maintenance of a higher pressure of the mediums in the subsequent upper slit sections than in the lower slit below 20 sections.

32. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that, as for this purpose in this tuunel arrangement, the successive semiconductor substrate portions, comprising at least nanometer wide, metal-filled semiconductor grooves in the dielectric top layer, were achieved without interruption. thereof and electrical connection portions therefor, in a device included in this semiconductor installation behind the exit of this tunnel arrangement because of continuous uninterrupted division of these successively supplied successive semiconductor substrate portions in both the length and length transverse direction means the establishment of successive groups of chips located side by side in the transverse direction on their output side.

A semiconductor chip as claimed in any one of the preceding Claims, characterized in that, as in a strip-shaped pressure compartment of the sub-tunnel block below a strip-shaped pressure wall portion thereof, the incorporation of a rotating camshaft arrangement for typically high-frequency vibrating at and moving down this pressure wall portion and therewith of the successive continuous semiconductor substrate portions passing along it, in this tunnel arrangement a number of semiconductor treatments using semiconductor treatment medium of these successive semiconductor substrate portions for the purpose of having contributed in an optimum condition thereof at the output of this tunnel arrangement and thereby of this semiconductor chip obtained therefrom.

34. A semiconductor chip as claimed in Claim 33, characterized in that, for this purpose, in a number of strip-shaped upper slit sections the continuous deposition of an optimum deposition of supply of at least co-semiconductor which took place in a previous strip-shaped section of the upper tunnel block took place. treatment medium using a fast up -20 and a subsequent slow downward displacement of these successive semiconductor substrate portions moving underneath.

35. A semiconductor chip as claimed in Claim 33, characterized in that, for this purpose, a number of successive or non-consecutive strip-shaped upper slit sections have taken place without interruption in a cleaning process of the treated semiconductor that took place in a previous strip-shaped upper slit section. top layer of the successive bottom-moving semiconductor substrate portions by means of a supply of at least partly the combination of evaporable liquid carrier medium and cleaning medium and removal of at least this cleaning medium into a subsequent strip-shaped drain and typically with a slow upward - and subsequent rapid downward displacement thereof.

36. A semiconductor chip as claimed in Claim 33, characterized in that for this purpose at least in a number of consecutive strip-shaped upper slit sections it has at least contributed to an etching process of an exposed semiconductor top layer portion of the successive one, substrate portions moving therebetween, typically having taken place a rapid upward and subsequent slow downward displacement thereof, and with the aid of at least one vaporizable liquid carrier medium having taken place in at least one preceding strip-shaped supply section in this upper tunnel block block and etching medium and in at least one discharge section in this block discharge of at least this etching medium.

37. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that, as therein, in a strip-shaped pressure compartment of the upper tunnel block above a strip-shaped pressure wall portion thereof, the incorporation of a rotating camshaft arrangement for the typical high-frequency vibrating up-and-down movement of this pressure wall section, in this tunnel arrangement, a number of semiconductor treatments have taken place in strip-shaped upper slit sections of these successive, continuous-moving semiconductor substrate sections underneath them by means of a preceding section strip-shaped feed section combination of low boiling liquid carrier medium and semiconductor treatment medium supplied in this block and discharge in a subsequent discharge sections, at least part of this treatment medium for the purpose of at least also contributing to an optimum condition at the exit of this tunnel-o and thus of this semiconductor chip obtained therefrom.

38. A semiconductor chip as claimed in Claim 37, characterized in that, for this purpose, in a number of strip-shaped upper slit sections the continuous deposition of an optimum deposition of supply of at least co-semiconductor that took place in a preceding strip-shaped section of the upper tunnel block has taken place. treatment medium with the aid of a slow upward and a subsequent rapid downward displacement of such a strip-shaped pressure wall section.

39. A semiconductor chip according to claim 37, characterized in that for this purpose a number of successive or non-consecutive strip-shaped upper slit sections have been subjected to a continuous cleaning process of the semiconductor upper layer of the successive upper slit section of the successive upper slit section. 10 moving semiconductor substrate portions underneath it by means of an uninterrupted supply of at least one cleaning medium and discharge of at least one of this cleaning medium and discharge of at least one of this cleaning medium in a preceding strip-shaped supply section in this upper tunnel block and wherein for this purpose a slow downward - and a subsequent rapid upward displacement of this strip-shaped pressure wall portion with the aid of this rotating camshaft arrangement. Characterized in that for this purpose in a number of successive strip-shaped upper slit sections, at least for this purpose, they have at least contributed to an etching process of an exposed semiconductor top layer of the successive, continuously moving semiconductor substrate sections underneath it using a previous strip-shaped feed section in this upper tunnel block has been subject to uninterrupted supply of at least this etching medium and where typically a slow upward and subsequent rapid downward displacement thereof have been maintained.

A semiconductor chip according to any one of the preceding Claims, characterized in that the height thereof is less than 0.2 mm.

42. Semiconductor chip according to one of the preceding

Claims, characterized in that it is further embodied such that it contains only one total dielectric layer and in its upper part the accommodation of multi-metal-filled, typically nanometer-wide grooves which are interconnected interconnected while obtaining an electrical circuit with electrical connection portions thereof.

43. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that it is further embodied such that it thereby comprises several superimposed dielectric layers, wherein in the top-topography of each layer the recording of multi with metal filled typically nanometer wide grooves which are interconnected to obtain an electrical circuit, the electrical circuits in these layers are connected to each other with at least substantially vertical interconnecting grooves and the upper electrical circuit contains electrical connection portions.

44. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that such a dielectric total layer consists of a number of superimposed and superimposed layers in this tunnel arrangement in its fused state and being such a layer. 20 realized from (sub) um large particles of a dielectric substance, for which purpose a continuous supply of the combination has taken place in a strip-shaped supply section of the upper tunnel block at the location of the central semiconductor treatment portion thereof of low-boiling liquid carrier medium and such particulate semiconductor substance, in a subsequent strip-shaped section with the aid of a vibrating element incorporated therein, which also acts as a heat source, vaporization of the low-boiling liquid carrier medium having taken place with a continuous discharge of the vapor produced in a subsequent strip-shaped medium discharge a section in the upper tunnel block having subsequently been followed by a substantially uniform precipitation of these particles, in a subsequent strip-shaped furnace section, a heat supply so small that at least almost exclusively the transfer of these particles in a fused state thereof and adhesion thereof to the previously applied dielectric layer has taken place and for the lower layer an anchoring or non-anchoring thereof to an already applied intermediate layer of adhesive substance and typically in a subsequent strip-shaped cooling. section has been uninterrupted in its cooling while having a solid state thereof.

45. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that it consists of an at least sufficiently heat-resistant plastic, typically Teflon, bottom layer and a layer applied to it in this tunnel arrangement and with or without (sub) pm high intermediate layer of adhesive substance-anchored dielectric layer, comprising at least also such metal-filled semiconductor grooves in its upper portion.

A semiconductor chip according to Claim 45, characterized in that such a dielectric layer is a semiconductor intermediate layer.

A semiconductor chip according to Claim 45, characterized in that such a dielectric layer is the dielectric top layer.

48. A semiconductor chip according to Claim 45, characterized in that such a semiconductor bottom layer is a relatively thick plastic film, which is continuously supplied for this purpose from a film storage roller near the entrance side of this tunnel arrangement.

49. A semiconductor chip as claimed in Claim 48, characterized in that a jim-high layer of liquid adhesive is applied to such a semiconductor substrate in a strip-shaped part of this tunnel.

A semiconductor chip according to Claim 49, characterized in that, on such a semiconductor adhesive layer, it is built up of a jim high metal intermediate layer.

A semiconductor chip according to any one of the preceding Claims, characterized in that such an intermediate layer of adhesion substance built up in this tunnel arrangement is realized from nanometer-sized particles thereof and wherein a strip-shaped supply section of the upper tunnel block is provided for this purpose of the central semiconductor handling portion thereof have been uninterrupted in the uninterrupted supply of the combination of low-boiling liquid carrier medium and such particles, in a subsequent strip-shaped section with the aid of a vibrating element incorporated therein, also functioning as heat source, vaporization of this low-boiling liquid medium with uninterrupted discharge thereof via a strip-shaped medium discharge section in this block, with the occurrence of a uniform deposition of these particles in a subsequent strip-shaped oven section of this block have taken place such a low heat supply that at least almost exclusively the bringing of these particles into a fused state thereof and in a subsequent strip-shaped cooling section have taken place without interruption in their cooling.

52. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that it consists of at least one metal substrate and an adhesive substance applied thereto in this tunnel arrangement and which is bonded to it with or without a (sub) µm high intermediate layer. -electric layer, comprising at least such metal-filled semiconductor grooves in its upper portion. A semiconductor chip according to Claim 51, characterized in that such a dielectric layer is a semiconductor intermediate layer.

54. A semiconductor chip according to Claim 51, characterized in that such a dielectric layer is the dielectric top layer.

55. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that in this tunnel arrangement a plastic intermediate layer is anchored on top of a metal bottom layer and such a dielectric top layer is anchored on this intermediate layer.

56. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that it also consists of a paper bottom layer which is continuously supplied for this purpose from a foil storage roller near the entrance side of this tunnel arrangement and wherein a dielectric top layer anchored thereon. is applied. 5 57. Semiconductor chip according to Claim 55, characterized in that it further comprises a metal intermediate layer applied to this paper substrate and anchored therewith in this tunnel arrangement and wherein said dielectric upper layer is anchored on said metal intermediate layer.

58. A semiconductor chip according to Claim 55 or 56, characterized in that it further comprises at least one dielectric intermediate layer arranged in this tunnel arrangement, typically consisting of a number of fused layers and also containing such metal-filled grooves in its upper-topography, which in this tunnel arrangement are connected by means of metal-filled connecting grooves to the metal-filled grooves effected in this dielectric upper layer.

59. A semiconductor chip according to any one of the preceding Claims, characterized in that it consists of a metal foil part as its semiconductor bottom layer, a plastic film applied thereon and anchored therewith as a semiconductor intermediate layer and at least one dielectric top layer anchored therewith. , containing at least co-such metal-filled grooves in its top-topography.

60. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that for these semiconductor layers constructed it is possible to use any suitable semiconductor substance for the purpose of using it as typically nanometer-sized semiconductor particles and this typically in 35 combination with liquid carrier medium with a continuous supply thereof.

61. A semiconductor chip as claimed in any one of the preceding Claims, characterized in that it is further designed such that, as in a device behind the tunnel arrangement, removal of the subsequent foil or tape portions took place as a temporary semiconductor substrate. of the successive semiconductor substrate portions moving therethrough, thus effecting successive semiconductor substrate portions with a dielectric backing thereof, since in a subsequent portion of this device, the effected portions thereof result in an embodiment with a dielectric bottom layer.

The semiconductor chip according to Claim 60, characterized in that it comprises a dielectric bottom layer with a metal intermediate layer thereon.

63. Method for the realization of a semiconductor chip, characterized in that at least the final phase of its manufacture then takes place in at least partly a semiconductor installation.

64. A method according to Claim 63, characterized in that in such a semiconductor installation such a semiconductor chip is effected in a device thereof, viewed in the longitudinal direction of this installation, subsequent semiconductor substrate portions, at least partly realized therein. .

A method according to Claim 64, characterized in that such successive semiconductor substrate portions are achieved exclusively in this semiconductor installation,

66. A method as claimed in any one of the preceding Claims, characterized in that, as for this purpose, in this semiconductor installation the incorporation of a semiconductor substrate transfer / treatment tunnel arrangement takes place, during the operation of this installation therein taking place at least substantially uninterruptedly therein. uniform linear displacement of these successive semiconductor 35 substrate portions therethrough from at least substantially the entrance side to the exit side thereof.

A method according to Claim 66, characterized in that, for this purpose, these successive semiconductor substrate sections are continuously connected in this semiconductor tunnel arrangement.

68. A method according to any one of the preceding Claims, characterized in that, at least partly for such successive semiconductor substrate sections, use is made of a foil with continuous infeed continuously fed therein through the entrance thereof during the operation of this semiconductor tunnel arrangement. a small thickness as an at least temporary semiconductor bottom layer thereof.

69. A method according to Claim 68, characterized in that, just like this semiconductor installation prior to the entrance of this semiconductor tunnel arrangement incorporated therein, a film storage container was provided for storing such a film with a thickness thereof typically less than 0, 1 mm and a storage capacity of typically at least 10,000 meters therefrom, thereby maintaining a continuous supply of successive film sections to this tunnel arrangement for a very long time.

70. A method as claimed in Claim 66, characterized in that, as for this purpose in this tunnel arrangement, the use of a continuous metal semiconductor substrate carrier / transfer belt as a temporary semiconductor substrate of these successive semiconductor substrate portions moving therethrough, having a roller arrangement near its entrance and exit sides and a drive device for rotating this rear roller, thereby maintaining a continuous movement of the successive belt sections through it during the operation of this tunnel arrangement.

71. A method according to any one of the preceding Claims, characterized in that at least partly for this purpose the application of at least some of the semiconductor methods is indicated and described in the Dutch Patent Application filed by the applicant at the same time as this Dutch Patent Application. application concerning such a semiconductor installation, a patent application concerning the semiconductor facility, in which this semiconductor installation is included and a patent application concerning a strip-shaped feed device for at least co-semiconductor treatment medium.

72. A method as claimed in any one of the preceding Claims, characterized in that in this tunnel arrangement the uninterrupted realization of successive semiconductor substrate sections with a height of typically less than 0.2 mm and thereby of the semiconductor chips obtained therefrom in the device included behind it.

73. A method according to Claim 72, characterized in that, at least partly for this purpose, in a strip-shaped part of this tunnel arrangement at the location of the central semiconductor treatment part thereof, the continuous realization of a typical nanometer-high layer of particles of a semiconductor dielectric substance, after which in a subsequent semiconductor treatment section the continuous taking place of an oven - treatment of the successive parts of this layer while obtaining a coiled condition thereof and in a subsequent strip-shaped section the continuous taking place of a cooling process while effecting this layer in its solid state as part of such a semiconductor chip.

74. A method according to claim 73, characterized in that for this purpose, in this semiconductor tunnel arrangement, the construction of a number of these nanometer-high layers applied in successive strip-shaped sections takes place, with typically after each of these applied the continuous occurrence of such a combination of an oven and a subsequent cooling process.

A method according to any one of the preceding claims, characterized in that the height of such an applied dielectric layer is less than 5 µm.

A method according to Claim 75, characterized in that there at the height of such a dielectric layer applied is less than 500 nanometers.

A method according to any one of the preceding claims, characterized in that only after building up a number of such superimposed dielectric layers using the combination of such a strip-shaped medium supply section, vibrating evaporator and medium discharge section, also such a combination of such a furnace treatment process taking place to effect a liquid layer of this dielectric substance and a subsequent cooling process to form a solid condition of such a semiconductor low.

78. Method as claimed in any of the foregoing Claims, characterized in that for this purpose at least partly such a nanometer-high dielectric layer is effected in this tunnel arrangement by continuous taking place in a strip-shaped medium supply section of the upper tunnel block thereof. the supply of the combination of low-boiling liquid carrier medium and nanometer-sized particles of such a dielectric substance and with the aid of a subsequent strip-shaped vibrating heat source, typically a transducer arrangement, at least also below the initial portion of this arrangement the gradual further evaporation of this low-boiling liquid medium with the simultaneous discharge of this evaporated medium into a subsequent strip-shaped discharge section 30, accompanied by a sufficiently uniform deposition of these particles. on the successive, uninterrupted moving semiconductors substrate portions under the effect of such a typical nanometer-high layer of particles of this dielectric substance.

A method according to Claim 78, characterized in that, like such a vibrating heat source, is a typical at least high-frequency vibrating strip-shaped pressure wall portion of said upper tunnel block and wherein typically with the aid of a rotating camshaft arrangement included in a strip-shaped pressure chamber part of this block, the occurrence of a rapid downward movement and a subsequent slow upward movement thereof.

A method according to Claim 78 or 79, characterized in that, also with the aid of this developed vaporous medium in combination with this vibrating strip-shaped heating device as a vibrating pressure wall, the maintenance of a mechanically contactless condition of such an applied layer is thereby maintained. dielectric substance with the upper tunnel block section above and also in this subsequent strip-shaped oven and cooling section.

81. A method according to Claim 80, characterized in that, among other things, maintaining a height of the portion of the upper gap, following this strip-shaped medium supply section for this combination of low-boiling liquid carrier medium and particles of dielectric substance, which is greater than the width of this supply section in the longitudinal direction of this tunnel arrangement.

82. A method according to Claim 80 or 81, characterized in that for this purpose at least partly under this strip-shaped vibrating heat source the use of an increasing height of this upper slit below it and this typically up to at least this subsequent medium discharge section .

83. A method according to any one of the preceding Claims, characterized in that, after having such a dielectric layer build-up on the subsequent semiconductor substrate moving through it in this tunnel arrangement, in a subsequent strip-shaped tunnel section continuing its flatness treatment with the aid of the portion of a rotary scraper located in the central section of the upper tunnel block.

A method according to Claim 83, characterized in that, in particular for the lower dielectric layer of these successive semiconductor substrate portions, such a number of repetitions of such a combination of a layer structure and a subsequent scraping process of the highest part thereof, which is finally brought about in a sufficiently flat condition of this total layer.

85. A method according to Claim 84, characterized in that in addition to the upper dielectric layer of this successive semiconductor substrate portions applied with the aid of such a scraping-off process, also achieving such a sufficient degree its flatness for the benefit of in a subsequent portion of this tunnel arrangement after the application of a um high exposure layer in subsequent tunnel portions the realization of multi-typical nanometer wide and deep metal-filled grooves while obtaining a semiconductor electrical circuit layer with electrical connection portions thereon.

A method according to any one of the preceding claims, characterized in that the height of such a single dielectric intermediate layer applied to said successive semiconductor substrate portions is less than 2 µm.

Method according to Claim 86, characterized in that the height of such a single applied semiconductor intermediate layer is less than 500 nanometers, typically less than 300 nanometers.

88. A method as claimed in any one of the preceding Claims, characterized in that, for such successive semiconductor substrate sections in a part of this tunnel arrangement, effecting a sufficiently flat bottom wall thereof using a sub-tunnel block, the top wall of which at least the central semiconductor treatment part is flat in at least the transverse direction thereof to a sufficient degree for this purpose.

A method according to Claim 88, characterized in that for this purpose it is brought above the wall section of the sub-tunnel block to less than 50 nanometers.

A method according to Claim 88 or 89, characterized in that no layer of liquid medium is applied in the subsequent sub-gap portions of the tunnel passage below the entire bottom wall of the subsequent semiconductor substrate portions moving therethrough.

A method according to Claim 90, characterized in that for this purpose the use of gaseous medium 15 in at least a substantial part thereof in the successive sub-gap sections of the tunnel passage under the successive semiconductor substrate sections maintaining mechanical contact of these substrate portions with these ultra-flat central top wall portions of the sub-tunnel block.

92. A method according to Claim 91, characterized in that for this purpose, at the location of such a tunnel section, the continuous maintenance of a higher pressure of the mediums in the subsequent upper slit sections than of the gaseous medium in the subjacent slits.

93. A method according to any one of the preceding claims, characterized in that, as for this purpose in this tunnel arrangement, the continuous realization of successive semiconductor substrate sections, comprising at least nanometer-wide, metal-filled semiconductor grooves 30 in its dielectric top layer and electrical connection portions in front, thereby in a device included in this semiconductor installation behind the exit of this tunnel arrangement by continuous division of these successive semiconductor substrate portions supplied therein continuously in both the longitudinal and transverse directions thereof. effecting successive groups of semiconductor chips adjacent to each other in the transverse direction on their output side.

A method according to any one of the preceding Claims, characterized in that, as in the case of a strip-shaped pressure compartment of the sub-tunnel block below a strip-shaped pressure wall part thereof, the incorporation of a rotating camshaft arrangement for the purpose of the typically high-frequency vibrating at and moving down this pressure wall portion and therewith of the successive continuous semiconductor substrate portions passing along it, in this tunnel arrangement a number of semiconductor treatments using semiconductor treatment medium of this substrate are performed in this tunnel arrangement successive semiconductor substrate portions for the purpose of contributing in an optimum condition thereof to the output of this tunnel arrangement and thereby of the semiconductor chips obtainable therefrom.

95. A method according to Claim 94, characterized in that, for this purpose, in a number of strip-shaped upper slit sections, the continuous occurrence of an optimum deposition of the supply of at least co-semiconductor treatment occurring in a previous strip-shaped section of the upper tunnel block medium with the help of a fast upward - and a subsequent slow downward displacement of these successive semiconductor substrate sections moving underneath.

96. A method according to Claim 94, characterized in that, for this purpose, in a number of strip-shaped or non-strip-shaped upper slit sections, a continuous cleaning process takes place of the semiconductor top layer of the successive strip-shaped upper-slit section. semiconductor substrate sections moving therebetween with the aid of, in a preceding strip-shaped feed section, supply of at least partly the combination of evaporable liquid carrier medium and cleaning medium and discharge of at least this cleaning medium in a subsequent strip-shaped discharge section and where typically with a slow upward movement - and a subsequent rapid downward movement thereof.

97. A method according to Claim 94, characterized in that for this purpose, in typically a number of successive strip-shaped upper slit sections, at least contributing to an etching process occurring therein of an exposed semiconductor top layer portion of the subsequent semiconductor moving underneath it substrate portions, typically with a rapid upward and subsequent slow downward displacement thereof, and with the aid of at least one vaporizable liquid carrier medium and etching medium occurring in at least one preceding strip-shaped feed section and in at least one drain section in this block drain of at least also this etching medium.

98. Method as claimed in any of the foregoing Claims, characterized in that, as in this case in a strip-shaped pressure compartment of the upper tunnel block above a strip-shaped pressure wall part thereof, the incorporation of a rotating camshaft arrangement for the typical high-frequency vibrating at and moving this pressure wall portion downwards, in this tunnel arrangement a strip number of semiconductor treatments therewith take place in strip-shaped upper slit sections of these successive, continuously moving semiconductor substrate sections along it with the aid of in a preceding strip-shaped supply section in a combination of low boiling liquid carrier medium and semiconductor treatment medium supplied in this block and in a subsequent discharge section discharge of at least a part of this treatment medium for the purpose of at least also contributing in an optimum condition thereof at the output of this tunnel arrangement and with this of this e 35 semiconductor chips to be produced therefrom.

99. A method according to Claim 98, characterized in that, for this purpose, in a number of strip-shaped upper slit sections the continuous deposition of an optimum precipitation of supply of at least co-semiconductor treatment medium that has taken place in a preceding strip-shaped section of the upper tunnel block takes place. with the help of a slow upward and subsequent rapid downward displacement of such a strip-shaped pressure wall section.

100. A method according to Claim 98, characterized in that, for this purpose, a number of successive or non-consecutive strip-shaped upper slit sections are used for the continuous cleaning of the semiconductor top layer of the successive upper slit section of the successive upper slit section. semiconductor substrate sections moving therebetween with the aid of continuous supply of at least one cleaning medium in a previous strip-shaped feed section in this upper tunnel block 15, and where a slow downward - and a subsequent rapid upward displacement of this strip-shaped pressure wall are typically provided for this purpose portion of the upper tunnel block using this rotating camshaft arrangement.

101. A method according to Claim 98, characterized in that for this purpose, in typically a number of successive strip-shaped upper slit sections, at least contributing to an etching process occurring therein of an exposed semiconductor top layer of the successive, continuously moving semiconductor substrate underneath it portions with the uninterrupted supply of at least this etching medium in a previous strip-shaped supply section in this upper tunnel block and where typically maintaining a slow upward and subsequent rapid downward displacement thereof.

102. A method according to any one of the preceding Claims, characterized in that the height of the semiconductor chip produced is less than 0.2 mm.

A method according to any one of the preceding Claims, characterized in that, as the successive semiconductor substrate portions contain only one total dielectric layer, the upper portion thereof effecting multi-metal-filled, typically nanometer-wide grooves , which are interconnected with each other while obtaining an electrical circuit with electrical connection portions thereof and thus effecting semiconductor chips with only one dielectric layer also as a top layer.

104. A method as claimed in any one of the preceding Claims, characterized in that like these successive semiconductor 10 substrate portions and thereby such semiconductor chips therein comprise several superimposed dielectric layers, while in the top-topography of each layer the realization of multi-metal filled, typically nanometer-wide grooves interconnected to provide an electrical circuit, the electrical circuits in these layers are connected to each other with at least substantially vertical interconnecting grooves and the upper electrical circuit electrical connection portions contain.

105. A method according to any one of the preceding Claims, characterized in that, as such a dielectric total layer consists of a number of superimposed urn high layers built up in this tunnel arrangement and becomes such a layer 25 is effected from (sub) µm large particles of a dielectric substance, the uninterrupted supply of the combination of 30 being carried out in a strip-shaped supply section of the upper tunnel block at the location of the central semiconductor treatment portion thereof low-boiling liquid carrier medium and such particles of semiconductor substance, in a subsequent strip-shaped section with the aid of a vibrating element incorporated therein, which also acts as a heat source, evaporation of the low-boiling liquid carrier medium with continuous discharge taking place of the vapor produced in a subsequent stripping medium discharge section i in the upper tunnel block taking place a substantially uniform precipitation of these particles, in a subsequent strip-shaped furnace section taking place such a low heat supply that at least almost exclusively bringing these particles into a fused state and its adhesion to the previously applied dielectric layer takes place and, for the lower layer, an anchoring or non-permanent anchoring thereof to an intermediate layer 10 of liquid adhesive substance, which is typically applied to the subsequent film or tape portions, with typically an subsequent strip-shaped cooling section, the uninterrupted occurrence of its cooling while effecting a solid state thereof.

106. A method according to any one of the preceding Claims, characterized in that the realization of such a semiconductor chip, which consists of an at least sufficiently heat-resistant plastic, typically Teflon, bottom layer and a layer applied to it in this tunnel arrangement and a dielectric layer anchored therewith, whether or not with a (sub) µm high intermediate layer adhesive substance, comprising at least also such metal-filled semiconductor grooves in the upper part thereof.

107. Method according to Claim 106, characterized in that a semiconductor intermediate layer is effected as such a dielectric layer.

A method according to Claim 106, characterized in that the dielectric top layer is effected as such a dielectric layer.

A method according to Claim 106, characterized in that, as such a semiconductor substrate is a relatively thick plastic film, it is supplied continuously for this purpose from a film storage roller near the entrance side of this tunnel arrangement.

110. A method according to claim 109, characterized in that the continuous build-up of a um high layer of liquid adhesive substance on the subsequent film sections moving through it in a strip-shaped part of this tunnel arrangement.

A method according to Claim 110, characterized in that in a number of successive strip-shaped sections of this tunnel arrangement on such a semiconductor bonding layer, the continuous construction of an urn-high metal intermediate layer takes place.

112. Method as claimed in any of the foregoing Claims, characterized in that such an intermediate layer of adhesive substance built up in this tunnel arrangement is realized from nanometer-sized particles thereof and wherein for this purpose in a strip-shaped supply section of the upper tunnel block at the location of the central semiconductor treatment part thereof, the uninterrupted supply of the combination of low-boiling liquid carrier medium and such particles, in a subsequent strip-shaped section with the aid of a vibrating element incorporated therein, also serving as a heat source, the continuous occurrence of evaporation of this low-boiling liquid medium with an uninterrupted discharge thereof via a subsequent strip-shaped medium discharge section in this block, with a sufficiently uniform deposition of these particles taking place in a subsequent strip-shaped oven section of this block taking place 25 of such a low heat input per unit of time that at least almost exclusively bringing these particles into a fused state thereof and in a subsequent strip-shaped cooling section taking place therein without interruption.

113. A method as claimed in any one of the preceding Claims, characterized in that, as it consists of at least one metal substrate and a diaphragm substance bonded thereto in this tunnel arrangement and anchored to it with or without a (sub) pm high intermediate layer. An electrical layer, which at least will contain such metal-filled semiconductor grooves in its upper portion.

A method according to Claim 113, characterized in that such a dielectric layer becomes a semiconductor intermediate layer.

The method according to Claim 113, characterized in that such a dielectric layer thereby becomes the dielectric top layer of the subsequent semiconductor substrate portions and thereby of such semiconductor chips produced therefrom.

116. A method according to any one of the preceding Claims, characterized in that in this tunnel arrangement a plastic intermediate layer is anchored on top of a metal bottom layer and such a dielectric top layer is applied to this intermediate layer.

117. Method as claimed in any of the foregoing Claims, characterized in that just as such a semiconductor chip 15 also consists of a paper bottom layer, the subsequent paper foil sections are supplied continuously for this purpose from a foil storage roller near the entrance side of this tunnel. arrangement and wherein a dielectric top layer is applied to it anchored.

118. A method according to Claim 117, characterized in that a metal intermediate layer is applied to this paper substrate in this tunnel arrangement, and wherein this dielectric top layer is applied to this metal intermediate layer anchored.

119. A method according to Claim 117 or 118, characterized in that like such successive semiconductor substrate sections further comprise at least one dielectric intermediate layer applied in this tunnel arrangement, typically consisting of a number of fused layers and comprising also such metal-filled grooves in their top-topography, these grooves are connected by means of metal-filled connecting grooves to the grooves to be effected in this dielectric top layer with metal-filling grooves.

120. A method according to any one of the preceding claims, characterized in that, as it consists of a metal foil part as a semiconductor bottom layer of the subsequent semiconductor substrate parts, a plastic foil part applied thereon and anchored therewith as a semiconductor intermediate layer and at least thereon a dielectric upper layer portion anchored therewith, which at least co-comprises such metal-filled grooves in its upper topography.

121. A method according to any one of the preceding Claims, characterized in that for these semiconductor layers to be built up, any suitable semiconductor substance is used for the purpose of making use of typically nanometer-sized particles and this typically in combination with liquid. or gaseous carrier medium with a continuous supply thereof.

122. Method as claimed in any of the foregoing Claims, characterized in that, as in a device behind the tunnel arrangement, the continuous removal of the subsequent foil or tape portions takes place as a temporary semiconductor substrate of the 4th successive semiconductor substrate moving through it - portions with thus the realization of successive semiconductor substrate portions with a dielectric substrate thereof, thereby obtaining, in a subsequent portion of this device, semiconductor chips having a dielectric substrate layer thereof.

123. A method according to Claim 122, characterized in that, in addition, these semiconductor chips will comprise a dielectric bottom layer with at least a metal intermediate layer thereon.

124. A method according to any one of the preceding Claims, characterized in that the possible application of any semiconductor production facilities, for the production of such semiconductor chips, for the production of semiconductor wafers, from which by dividing it, obtaining semiconductor chips, already widely used semiconductor treatment, application and penetration systems of semiconductor substances in an adapted capacity / condition thereof. 1037063