KR100196686B1 - Apparatus for fast copy between frame buffers in a double buffered output display system - Google Patents

Abstract

The following components: a first frame buffer; A second frame buffer; An apparatus for transmitting data to an output display device with a second frame buffer; And a device composed of the following two devices, namely, a device for writing new data only to the first frame buffer, and reading data from the first frame buffer and writing read data to the second frame buffer during the same operation. And an apparatus for controlling the transfer of data to each frame buffer.

Description

Device for high speed copying between frame buffers in dual buffer output display system

1 is a block diagram illustrating a prior art arrangement for reducing the cost of a double buffering arrangement.

2 is a block diagram of an arrangement in accordance with the present invention for providing double buffering.

[Background of invention]

[Field of Invention]

The present invention relates to a computer output display device, in particular a method and apparatus for removing frame tearing from a computer output display using inexpensive double buffering.

[History of Conventional Technology]

Typical computer systems generate data displayed on an output display. This output display, typically a cathode ray tube that produces many full screens in turn, is so fast that in the eyes of the observer it appears as if a displayed program is displaying a certain action when it can produce such an action.

To calculate the individual images (frames) that are displayed in turn, data is written to the frame buffer.

The frame buffer stores information about each position (each pixel) on the display that can be illuminated to yield the entire screen.

For example, the display may display pixels with about 1,000 horizontal lines each having approximately 1,000 pixels.

All this information in each frame is written to the frame buffer before being scanned into the display. When data describing the telephone is present in the frame buffer, the frame can be sent to the display.

Typically, data is transferred from the frame buffer by one pixel and line by line to the display starting at the top left corner of the display and progressing horizontally from left to right in the direction below the bottom right corner of the display. In order for the image to appear continuously on the output display, the frames following the frame buffer must be continuously scanned to the output display at a rate of 30 frames per second or every two or more.

While each frame of data is scanned into the display, new data appearing in the next frame must be sent to the frame buffer.

Typically, only changing data replaces the old data in the frame buffer with a position that represents that pixel's position on the screen.

All unchanged data remains in the frame buffer unchanged.

New data displayed in a frame can be written to any part of the frame buffer at any time.

Two ported dynamic RAMs (VRAMs) are used in the frame buffer to allow information to be written to the frame buffer and simultaneously scanned into the output display outside the frame buffer. Data is recorded through one port and scanned into the display through the other. VRAM is more expensive than a typical dynamic RAM because it provides two ports that require a significant number of transistors.

If information is scanned into the display and placed in the VRAM frame buffer, the information scanned into the display is received from the frames that have been displaced twice in succession. For example, if the scan proceeds at a faster rate than the data written to the frame buffer, and if a portion of the changing frame buffer is scanned to the display, then a portion of the display must be on the first frame, and some The above will undoubtedly be in the second slow frame.

The display of the portion of the frame that has been displaced twice at the same time is called frame tearing. This can be changed where the information that allows the image to be distorted as a whole changes quickly, as in real-time video.

To eliminate frame tearing, double buffering is used.

Double buffering uses two full frame buffers, each of which can store one previous frame. Data is written to one frame buffer and scanned from the other frame buffer to the display. In its simplest form, this is accomplished by using a pair of VRAM frame buffers and multiplexing the data in one or another frame buffers to the display.

In this form, data is never written to the frame buffer for the time its data is scanned to the display.

Once fully described, it can be alternately scanned into a display and all further data can be written to another frame buffer.

Frame tearing cannot occur because data is never written to the frame buffer while its contents are scanned into the display.

This simple form of double buffering is rather expensive because it uses two full VRAM frame buffers, and has a control signal generation circuit and a multiplexer for replacement between the two frame buffers.

One of the primary goals of a computer designer is to allow a large number of individual programs to run on a computer and display on the computer's output display. Typically, when many individual programs are displayed on a computer output display, each individual program typically appears in a window, which is a rectangular area of the screen that can be moved around, enlarged and reduced in size, and otherwise manipulated. If a large number of programs can be executed and displayed in a large number of windows at the same time, the work accomplished using a computer can be accelerated.

Typically, information recorded in individual windows by different individual programs is recorded at different speeds.

For example, information directed to a window displaying real-time video changes very quickly, while information typed from the keyboard to a word processor program displayed in another window changes more slowly.

Thus, the program changes from program to program at the rate at which the frame changes.

The simplest form of double buffering described above is very useful when a single program is executed on an output display.

However, where a large number of programs are executed simultaneously in different windows on the same output display, this form of double buffering is not sufficient.

The reason for this is that the simple form of double buffering requires that the entire contents of each frame buffer be scanned into the display.

If data is written in a large number of windows at the same speed, the timing at which the writing occurs varies from window to window; It is very difficult to adjust the write timing so that no write occurs for the frame buffer scanned into the display.

To solve this problem, an improved form of double buffering was used to add another buffer called the window recognition (ID) plane.

The window recognition plane provides a storage location for each pixel displayed on the output display. Stored at these locations in the window ID plane is the identifier of the window to which each pixel of data is connected.

By using this plane, the pixel is selected to be displayed at any time from any buffer.

Thus, the window ID plane can be used to scan into display data from any window where no data was recorded at the scan time.

Thus, this form of double buffering allows frame tearing to be eliminated, where multiple activation windows appear simultaneously on the output display.

This second form of double buffering not only uses two full VRAM frame buffers and circuits to control and multiplex from the two frame buffers to the display, but also circuits for selecting the displayed pixels based on the window in which they appear. It is very expensive because it adds an ID plane containing memory to each pixel of the display.

The experimenter has sought arrangements to reduce the cost of the 2 VRAM buffer and control circuitry for multiplexing between 2 VRAM frame buffers or between individual pixels of the first and second forms of double buffering.

One form of double buffering that has been used in the prior art to reduce costs replaces a single ported DRAM frame buffer with one of the VRAM frame buffers and eliminates control circuitry to scan from one of the frame buffers to the display. Instead, all frames are scanned from the signal VRAM frame buffer to the display; All new data is written to the DRAM frame buffer.

Once written, data in the DRAM frame buffer is transferred from the DRAM frame buffer to the VRAM frame buffer by the central processing unit.

This requires the reading of the DRAM by a processor followed by the writing of data to the VRAM frame buffer.

Typically this can happen in blocks of large data, such as processors that can transfer on their buses (eg 32 bits); The transmission is repeated over and over until completion.

This type of double buffering is much cheaper than other types because less expensive DRAM replaces one of the VRAM frame buffers and the control circuitry for multiplexing is eliminated. This arrangement is also useful because it works well with software that forms the X11 standard (X window), which does not expect to see more than a single frame buffer, and stores the information transferred to a frame buffer in a region of main memory. . For this software, DRAM frame buffers appear to be part of the main memory device. This arrangement also provides the benefit of being transferable from the visible DRAM frame buffer to the VRAM frame buffer because the CPU can selectively control the area transferred.

However, the transfer of information from the DRAM frame buffer to the VRAM frame buffer is relatively slow compared to the typical scan rate to the display.

Thus, it is possible to write to the VRAM frame buffer so that information occurs at the position scanned into the display; There is a problem called frame tearing.

If writing has proceeded at a faster rate than scanning to the display, it is possible to eliminate this problem by writing below the scanned row and utilize cheap circuits to achieve double buffering.

[Summary of invention]

Accordingly, a first object of the present invention is to reduce the cost of prior art double buffering arrangements while retaining the ability to eliminate frame tearing.

A second object of the present invention is to increase the transfer rate between frame buffers in the system, where only information from one of the two frame buffers is scanned into the output display.

The above and third objects of the present invention are directed to the following means: first frame buffer; A second frame buffer; Means for transferring data from the second frame buffer to the output display device; And means composed of the following two means, ie means for writing new data only to the first frame buffer, and for reading data from the first frame buffer and writing read data to the second frame buffer during the same operation. It is realized in an output display system which consists of means for controlling the transfer of data to each frame buffer with means.

The above and fourth objects of the present invention will be better understood by reference to the following detailed description taken in conjunction with the drawings, wherein like elements are referred to by the same reference throughout the several views.

[Comment and nomenclature]

Some portions of the detailed description that follows are represented in the cell of symbolic representations of operations on data bits within computer storage.

These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The action requires the actual manipulation of their actual quantities.

Typically, though not required, these quantities take the form of memory, transmission, combination, comparison and other operable electrical and magnetic signals.

It proves sometimes convenient to refer to signals such as bits, values, elements, symbols, characters, terms, numbers, etc., mainly because of common usage.

However, it should be borne in mind that both these and similar terms are associated with appropriate actual quantities and are simply convenient labels employed on these quantities.

Moreover, manipulations performed are commonly referred to in terms, such as additions or comparisons, which are commonly associated with mental manipulations performed by human operators.

None of these capabilities of the human operator is necessary or desirable in most cases of any of the operations described herein to form part of the present invention; The operation is a machine operation. In most cases, you need to keep in mind the difference between how you operate your computer and how it calculates itself.

The present invention relates to the steps of an apparatus and method for operating a computer in processing an electrical or other (eg mechanical, chemical) real signal to generate another desired real signal.

Referring now to FIG. 1, a circuit 10 constructed in accordance with the prior art is described. The circuit 10 only includes the base of the circuit necessary to provide data to the output display terminal used in a typical computer system.

Other parts necessary to provide the operation of the computer are known to those skilled in the art and are not shown in the drawings.

Described in FIG. 1 is a central processing unit 12 representing circuitry for controlling the operation of the entire computer system and providing the displayed data on the output display 14. In order to achieve the transfer of data from the central processing unit 12 to the output display 14, the first and second frame buffers 16 and 17 are utilized.

In the simplest form of double buffering described above, data is written to one frame buffer in the central processing unit 12 and computed from the other device to the display 14.

In its simplest form, this is accomplished by using a pair of VRAM frame buffers and multiplexing all frames of data from one of the frame buffers 16 and 17 to the display by means of a multiplexer 19.

The data transmitted by the multiplexer 19 is converted by the D / A converter 20 from digital to analog form and scanned into the display.

In this form of double buffering, data is never written to frame buffer 16 or 17 while time data is scanned from its frame buffer to the display. Once a frame has been completely written to frame buffer 16 or 17, the data in that frame buffer are alternately scannable to the display; Data can be written in another frame buffer.

Frame tearing cannot occur because the data is not written to the frame buffer while the content of the data is scanned to the display.

The completion of this form of double buffering is rather expensive because both use two frame buffers constructed of expensive VRAM.

Moreover, the arrangement requires a control signal to generate a circuit for selecting multiplexed information for the display from the frame buffer and a multiplexer 19 for opening and closing between the two frame buffers 16 and 17.

To reduce these costs, prior art arrangements have replaced VRAM used in frame buffer 16 with DRAM.

Because the DRAM is single potted, the frame buffer 16 does not provide an immediately scannable output to the display 14. Thus, the lines from the frame buffer 16 to the multiplexer 19 (shown at points in the figure) are removed.

Since no output is sent from the frame buffer 16 to the multiplexer 19, the multiplexer 19 (shown again in the outline shown by the dots) is also removed.

Without the multiplexer, the control circuitry for selecting one or the other of the frame buffers 16 or 17 for scanning to the display 14 is also unnecessary and eliminated.

This substantially reduces the cost of the system.

All new data is written to the frame buffer 16 by the central processing unit 12.

All data is scanned from frame buffer 17 to display 14.

Once the frame stored in the frame buffer 16 is changed, the frame is transferred to the frame buffer 17. To achieve this transfer, the control circuitry 23 in the central processing unit 12 selects a portion of the read frame buffer 16, typically of any amount or 32 bits, typically equal to the width of the bus.

This data is read and latched into the central processing unit 12.

This readout typically requires three clock periods for row addressing by the control circuit 23 and four clock periods for column addressing.

The central processing unit 12 then writes the information read from the frame buffer 16 into the frame buffer 17.

This typically requires three clock cycles for row addressing by the control circuitry 23 in the frame buffer 17 and again three clock cycles for column addressing in the frame buffer.

The additional clock time for column addressing in the frame buffer 16 during the read operation is read by the central processing unit 12 of the frame buffer 16 and the frame buffer 17 so that the device does not access the bus at the same time. Is actually needed to provide a dead cycle to the bus between write cycles.

Thus, a total of 13 or more clock cycles are repeated for a time sufficient to transfer positive data (which may be as large as the previous frame) in this array. As can be visualized, this is a relatively slow process, allowing only about 20 frames per second to be transmitted when copying the entire frame.

A typical display, on the other hand, can receive information from the frame buffer 17 at a rate of 76 frames per second.

Scanning proceeds at about three times the speed of what is described with frame buffer 17.

therefore. This less expensive arrangement allows scanning to the display to catch the writing of data from frame buffer 16 to frame buffer 17 so that frame tearing can occur.

In order to eliminate the problem of frame tearing in this less expensive double buffering system, the arrangement of the present invention described in FIG. 2 has been devised.

The arrangement comprises a central processing unit 27, a first frame buffer 28 configurable to VRAM, a second frame buffer 29 configurable to DRAM, a D / A converter 31, and an output display 33. Doing.

The arrangement 25 acts in a conventional manner, such as with the minimal cost of FIG. That is, all new data is written to the DRAM frame buffer 29 by the central processing unit 27. All data is scanned from the VRAM frame buffer 28 to the display 33. The new data is once described as a frame stored in the frame buffer 29, and the frame is transferred to the frame buffer 28.

To achieve this transfer, the central processing unit 27 reads the selected negative of the frame buffer 29, which is typically 32 bits, and writes the data to the frame buffer 28.

This process is continued while the desired amount of data is transferred.

Compared to the time taken to transfer from the frame buffer 16 in the arrangement of FIG. 1 to the frame buffer 17, the arrangement of the present invention transfers about four times the data at high speed. Thus, about 80 frames per second can tear off frames.

Fast copying of data from frame buffer 29 to frame buffer 28 is accomplished in the following manner.

Rather than a single control circuit 23 for controlling the selection of data accessed in both frame buffers 16 and 17 as in the arrangement of FIG. 1, array 25 is internal to CPU 27 (or frame buffer). A pair of individual control circuits are provided at (28 and 29) and other devices for controlling the rendering therefrom.

The first of these circuits 34 controls the access of the frame buffer 29, and the second circuit 35 controls the access of the frame buffer 28.

By utilizing the individual control circuits 34 and 35, the frame buffers 28 and 29 are simultaneously accessible. The data is still only written into the frame buffer 29 by the central processing unit upon rendering. However, when data is read from the frame buffer 29 and written to the frame buffer 28, the control circuit 34 selects an appropriate row and column address for the frame buffer 29, and the control circuit 35 controls the frame. Select the same row and column address in buffer 28.

The control circuit 34 then reads the data accessed in the frame buffer 29 and places it on the bus where the information is written in the frame buffer 28 with the same access address. Data is not latched into the central processing unit 27; Thus no dead cycle is needed for the rotated bus, so that no two devices attempt to access the bus at the same time.

This arrangement saves a lot of access time.

First, there are no independent read and write cycles, so that the rows and columns that you select for two frame buffers occur simultaneously, taking up half of that time.

Thereafter, no clock cycle is needed to rotate the bus.

Finally, since the control circuit does not need the first 1 frame buffer and then nothing else, it is practically possible to latch the row address in the first transfer. This removes the time for advancing row access for the remainder of any particular row displayed.

Thus, after the first piece of data has been accessed, the remaining transfer from each row requires only a single three clock to access time with the reading of the frame buffer 29 and the writing of that data to the frame buffer 28.

This is less than one quarter of the time required by prior art circuits.

Since the time required to copy from the frame buffer 29 to the frame buffer 28 is reduced to less than one quarter, more than four times more data than many previous frames use the present invention as in the prior art double-borough arrangement. It can be described as a frame buffer 28. Thus, while the maximum scan rate from the frame buffer is 76 frames per second, more than 80 frames per second can be written into the frame buffer 28.

At this rate, scanning cannot catch writes to the frame buffer 28, and frame tearing will not occur.

To be sure, the copy does not catch the scan, but is needed to start all the copies between buffers 29 and 28 at the point displayed below the point where no scan occurs.

This is simply accomplished by sending to the row position of the scan in the circuit that controls the scan of the information from the frame buffer 28 to the display.

Although it has been described in terms of the preferred embodiments of the present invention, it will be appreciated that various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present invention.

Accordingly, the present invention should be measured on the conditions of the following claims.

Claims (4)

The following components: a first frame buffer; A second frame buffer; Means for transmitting data from the second frame to the output display device; And means composed of the following two means, i.e., means for writing new data only to the first frame buffer, and for reading data from the first frame buffer and writing the read data to the second frame buffer during the same operation. And means for controlling the transfer of data to each frame buffer having means. 2. The apparatus of claim 1, wherein the means for reading data from the first frame buffer and writing the read data to the second frame buffer during operation comprises: addressing row accesses of the first and second frame buffers; And means for simultaneously selecting and controlling means for simultaneously selecting addresses for column access of the first and second frame buffers. The following steps: transferring new data displayed in the first frame buffer, reading the data from the first frame buffer to update the display, and simultaneously writing the data into the second frame buffer, and Transmitting a frame of data from a two frame buffer to an output display. 4. The method of claim 3, wherein the step of writing the data to the second frame buffer concurrently with reading the data for updating the display from the first frame buffer determines the address for row access of the first and second frame buffers. At the same time, selecting the address for column access of the first and second frame buffers.